[openfirmware] r1175 - cpu/x86 cpu/x86/pc cpu/x86/pc/biosload cpu/x86/pc/olpc cpu/x86/pc/olpc/via dev/via/unichrome
svn at openfirmware.info
svn at openfirmware.info
Fri May 8 09:56:11 CEST 2009
Author: wmb
Date: 2009-05-08 09:56:10 +0200 (Fri, 08 May 2009)
New Revision: 1175
Added:
cpu/x86/apic.fth
cpu/x86/pc/olpc/via/ioinit.fth
cpu/x86/pc/olpc/via/romstart.bth
cpu/x86/pc/olpc/via/startcacheasram.fth
cpu/x86/pc/olpc/via/startcbgfxinit.fth
cpu/x86/pc/olpc/via/startcfgio.fth
cpu/x86/pc/olpc/via/startcominit.fth
cpu/x86/pc/olpc/via/startdraminit.fth
cpu/x86/pc/olpc/via/startgfxinit.fth
cpu/x86/pc/olpc/via/starthostctl.fth
cpu/x86/pc/olpc/via/startmacros.fth
cpu/x86/pc/olpc/via/startmemtop.fth
cpu/x86/pc/olpc/via/startmtrrinit.fth
cpu/x86/pc/olpc/via/startusdelay.fth
dev/via/unichrome/vgamodes.fth
Modified:
cpu/x86/pc/apic.fth
cpu/x86/pc/biosload/config.fth
cpu/x86/pc/linux.fth
cpu/x86/pc/mmusetup.fth
cpu/x86/pc/olpc/versions.fth
cpu/x86/pc/olpc/via/addrs.fth
cpu/x86/pc/olpc/via/config.fth
cpu/x86/pc/olpc/via/devices.fth
cpu/x86/pc/olpc/via/fw.bth
cpu/x86/pc/olpc/via/olpc.bth
cpu/x86/pc/olpc/via/pcinode.fth
cpu/x86/pc/olpc/via/rmstart.fth
cpu/x86/pc/olpc/via/romreset.bth
cpu/x86/pc/olpc/via/versions.fth
cpu/x86/pc/report.fth
cpu/x86/pc/resetend.fth
dev/via/unichrome/loadpkg.fth
dev/via/unichrome/unichrome.fth
Log:
OLPC Via version - Omnibus checkpoint with better Linux support,
text mode support for display, and a build option for using
coreboot memory init code.
Added: cpu/x86/apic.fth
===================================================================
--- cpu/x86/apic.fth (rev 0)
+++ cpu/x86/apic.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,288 @@
+purpose: Advanced Programmable Interrupt Controller driver
+\ See license at end of file
+
+0 0 " fee00000" " /" begin-package
+
+" apic" name
+
+\ Docs:
+\ "Intel Architecture Software Developer's Manual", Volume 3, chapter 7.5:
+\ "Advanced Programmable Interrupt Controller (APIC)"
+\ See linux/include/asm-i386/i82489.h for further details.
+
+: apic-base-msr! ( l -- ) 0 h# 1b msr! ; \ High 32 bits are unused
+: apic-base-msr@ ( -- l ) h# 1b msr@ drop ;
+
+: apic-on ( -- ) apic-base-msr@ h# fff and h# 800 or apic-mmio-base or apic-base-msr! ;
+: apic-off ( -- ) apic-base-msr@ h# 800 invert and apic-base-msr! ;
+
+0 value apic-base \ Needs to be mapped and set
+
+: apic! ( l reg -- ) apic-base + l! ;
+: apic@ ( reg -- l ) apic-base + l@ ;
+: apic-set ( mask reg -- ) dup apic@ rot or swap apic! ;
+: apic-clr ( mask reg -- ) dup apic@ rot invert and swap apic! ;
+
+\ Support
+
+code cpu-capabilities ( -- n )
+ 1 # ax mov
+ cpuid
+ dx push
+c;
+: apic-present? ( -- flag ) cpu-capabilities h# 200 and 0<> ;
+: soft-on ( -- )
+ h# f0 apic@
+ h# 100 or \ APIC on
+ h# 200 invert and \ Focus processor checking
+ h# ff or \ Spurious IRQ vector ff
+ h# f0 apic!
+;
+
+\ Methods
+
+: id! ( id -- ) d# 24 lshift d# 20 apic! ;
+: id@ ( -- id ) d# 20 apic@ d# 24 rshift ;
+: lvt0-disable-irq ( -- ) h# 10000 h# 350 apic-set ; \ Disable LINT0
+: lvt0-enable-irq ( -- ) h# 10000 h# 350 apic-clr ; \ Enable LINT0
+: lvt1-disable-irq ( -- ) h# 10000 h# 360 apic-set ; \ Disable LINT1
+: lvt1-enable-irq ( -- ) h# 10000 h# 360 apic-clr ; \ Enable LINT1
+: timer! ( l -- ) h# 380 apic@ drop h# 380 apic! ;
+: timer@ ( -- l ) h# 390 apic@ ;
+: timer-disable-irq ( -- ) h# 10000 h# 320 apic-set ; \ Dis IRQ when timer passes 0
+: timer-enable-irq ( -- ) h# 10000 h# 320 apic-clr ; \ Dis IRQ when timer passes 0
+: timer-periodic ( -- ) h# 30000 h# 320 apic-set ;
+: timer-one-shot ( -- ) h# 320 apic@ h# 20000 invert and h# 10000 or h# 320 apic! ;
+: timer-irq! ( vector -- ) h# 320 apic@ h# ff invert and or h# 10000 or h# 320 apic! ;
+: perf-disable-irq ( -- ) h# 10000 h# 340 apic-set ; \ Dis IRQ when perf timer passes 0
+: perf-enable-irq ( -- ) h# 10000 h# 340 apic-clr ; \ Dis IRQ when perf timer passes 0
+: perf-irq! ( vector -- ) h# 340 apic@ h# ff invert and or h# 10000 or h# 340 apic! ;
+
+: ack-irq ( -- ) h# f0 apic@ drop 0 h# b0 apic! ; \ b0 is eoi
+
+: open ( -- okay? )
+ apic-base 0= if
+ apic-mmio-base h# 400 " map-in" $call-parent to apic-base
+ apic-on
+ then
+ true
+;
+: close ( -- ) ;
+
+end-package
+
+0 0 " fec00000" " /" begin-package
+
+" io-apic" name
+
+0 value io-apic-base
+: io-apic@ ( index -- l ) io-apic-base c! io-apic-base h# 10 + l@ ;
+: io-apic! ( l index -- ) io-apic-base c! io-apic-base h# 10 + l! ;
+
+\ Debugging
+
+: .apic-mode ( low -- )
+ 8 rshift 7 and case
+ 0 of ." Fixed " endof
+ 1 of ." LowPri " endof
+ 2 of ." SMI " endof
+ 3 of ." Res3 " endof
+ 4 of ." NMI " endof
+ 5 of ." Init " endof
+ 6 of ." Res6 " endof
+ 7 of ." Ext " endof
+ endcase
+;
+
+: .apic-irq ( int# -- )
+ 2* h# 10 + dup io-apic@
+ ." Vec: " dup h# ff and 2 u.r space
+ dup .apic-mode
+ dup h# 800 and if ." Logical " else ." Physical " then
+ dup h# 1000 and if ." Pending " else ." Idle " then
+ dup h# 2000 and if ." Low " else ." High " then
+ dup h# 8000 and if
+ ." Level " dup h# 4000 and if ." IRR " else ." EOI " then
+ else ." Edge " then
+ h# 10000 and if ." Masked " else ." Open " then
+ 1+ io-apic@
+ ." EDID: " dup d# 16 rshift h# ff and 2 u.r
+ ." Dest: " d# 24 rshift h# ff and 2 u.r
+ cr
+;
+: .apic-irqs ( -- )
+ push-hex
+ 1 io-apic@ d# 16 rshift h# ff and 1+ 0 do
+ i 2 u.r space i .apic-irq
+ loop
+ pop-base
+;
+
+\ Methods
+
+: trigger-irq ( irq# -- ) io-apic-base h# 20 + c! ;
+: eoi ( vector -- ) io-apic-base h# 40 + c! ;
+
+: open ( -- okay? )
+ io-apic-base 0= if
+ io-apic-mmio-base h# 80 " map-in" $call-parent to io-apic-base
+ then
+ true
+;
+: close ( -- ) ;
+
+end-package
+
+0 value apic-ih
+0 value io-apic-ih
+stand-init: APIC
+ " /apic" open-dev to apic-ih
+ " /io-apic" open-dev to io-apic-ih
+;
+
+0 [if]
+\ For tdcr (3e0):
+\ Divisor: 1 2 4 8 16 32 64 128
+\ Value : b 0 1 2 3 8 9 a
+
+\ Timer base low bit at bit 18
+\ Timer base div is mask 2
+
+\ Other regs:
+\ LVR 0x30
+\ GET_APIC_VERSION(x) ((x)&0xFF)
+
+\ TPR 80 Task Priority, 000000xx only service interrupts higher than this value
+\ APR 90 Arbitration Priority, used during bus arbitration
+\ PPR a0 Processor Priority, depends complexly on TPR and incoming interrupt
+
+\ LDR 0xD0 Logical Destination Register II000000 II is logical APIC ID
+\ DFR 0xE0 Destination Format Register M0000000 M is the model (F:flat or 0:cluster)
+\ LVTERR 0x370
+\ TDCR 0x3E0
+\ ICR 0x310 Generate local interrupt by writing
+
+\ IRR 200 - 270 (8 registers - 256 bits) Request - bit is set if interrupt pending
+\ ISR 100 - 170 (8 registers - 256 bits) Service - INTA latches highest priority bit
+\ TMR 180 - 1F0 (8 registers - 256 bits) Bit is set for level, clear for edge. EOI commands sends EOI msg to all IOAPIC
+
+20 0
+30 50014
+80 f0
+d0 0
+e0 ffffffff
+f0 10f
+320 10000 Timer Masked off
+340 10000 PCINT Masked off
+350 700 LINT0 vector 0 mode ExtINT (111) Edge Trigger Active High
+360 400 LINT1 vector 0 mode NMI (100) Edge Trigger Active High
+370 10000 ERROR Masked off
+380 0
+390 0
+
+Io apic
+259 9 (def 08) bit 0=1 enabe MSI Flat Mode Support
+
+25c 10 APIC D11 is masked to 1, cluster mode disabled
+268-26f 0 .. 0 Priority of all CPUs = 0
+296 a - bit 0 = 0 Assert HDPWR# for both read / write cycles (other bits are enable V4 fast TRDY, dynamic HDPWR#)
+297 1 - bit 1 = 0 Don't pipeline APIC requests, bit 0 = 1 enable redirect low priority apic reqs to CPU 0
+386 3f - bit 5 ena apic low interrupt arb, bit 4 io apic fec80000 - fecf.ffff to PCI2, bit 3 host snoop, 2 enable top sm mem, 1 enable sdio support for using system memory 4kbytes, 1 enable compatible smm
+485 5 - bit 1 = 0 free-running apic clock (not dynamic) [Reserved in 855]
+488 0 - bits 1 and 0 free running apic clocks [Reserved in 855]
+4a2 d6 - bit 3 = 0 disable apic interface power management [Reserved in 855]
+
+-- Following registers in D0F5 are [Reserved in 855]
+540 4c (default) - bit 7 disable legacy apic, c is irrelevant if disabled
+541 0 (def) - irrelevant if 540 disabled
+542 3 (def) - bit 3 disable intx transparent mode, bit 2 dis apic nonshare mode, bit 1 ena APIC interrupt disable, bit 0 enabe boot interrupt function
+544 0 (def) - bit 7 boring, bit 1 dis pcie dev uses msi cycle wake up system from c3, bit 0 apic data voltage 2.5v
+-- End reserved
+
+
+io apic regs: fec0.0000
+00 index register for indirect regs
+10 data register for indirect regs
+20 write the IRQ #
+40 EOI WO
+
+indirect io apic regs
+00 1000000 IOAPIC ID is 1
+01 178003 (RO) version
+02 1000000 Arb ID is 1
+03 1 Front side bus message delivery
+10,11 0100.0000 . 0001.0000 DD00 . 0000 . 000 ooom . tips MVV
+..
+3e,3f 0100.0000 . 0001.0000
+ DD is destination APIC ID in physical mode (since bit 11 = 0)
+ m = 1 means masked
+
+
+8848 0 bit 7 = 0 address bit 2 of FSBis not force low (default)
+884d 1 bit 3=0 disable some funny thing about APCI Ch0 ext interrupt delivery (def), bit 2=0 dis ser irq always shared in APIC mode (def)
+
+PnP routing
+8854 00 non-inverted PCI INT#
+8855 a0 INTA IRQ10
+8856 b9 INTC IRQ11, INTB IRQ9
+8857 a0 INTD IRQ10
+
+APIC Mode INTA-H
+PIRQ16 A
+PIRQ17 B
+PIRQ18 C
+PIRQ19 D
+PIRQ20 E
+PIRQ21 F
+PIRQ22 G
+PIRQ23 H
+
+8858 60 (def 40) bit 6 ena Internal APIC
+885b 53 (def 01) bit 6 port 80 to LPC, bit 4 ena APIC clock gating, bit 3=0 dis bypass apic de-assert Msg, bit 1 res, bit 0 ena dynamic clock stop
+886c 00 (def) bit 3 dis apic positive decode
+88b0 30 (def 08) bits 5,4 ena uart 2,1, bit 3=0 disable apic C4P State Mode Control
+88e7 80 (def 00) bit 7 enable apic cycle reflect to all bus master activity effective signal
+88ec 00 (def 00) bits 7:4=0 disable V1 interrupt routing
+
+PMIO+65 bit 7 set to 1 to enable APIC interrupt wake up system from C4P state
+
+8f73 01 (def 00) bit4=0 enable APIC cycle block p2c write cycle (def), bit 0=1 enable pci broken master timer
+8f74 0c (def 00) bit3=1 lock cycle issued by cpu block p2c cycles, bit2=1 APIC FSB directly up through CCA (not PCI) and 7c[1] must also be set [Bit 2 is reserved in 855]
+8f7c 02 (def 02) bit2=1 APIC FSB directly up through CCA (not PCI) and 74[2] must also be set
+
+8f80 07 (def 00) bit0=1 APIC cycle blocks HDAC upstream write
+
+8fe0 93 (def 40) various. bit 3=0 dis APIC cycle flush HDAC Upstream Write Cycle [Reserved in 855]
+8fe6 3f (def 01) bit5 supposedly reserved, bit4=1 split fecxx.xxxx range btw PCI1 and PCI2, bit3=1 processor MSI support enable, bit2=1 Top SMM enable, bit1=1 High SMM enable, bit0=1 Compatible SMM enable
+
+
+
+When enable internal APIC, PCI devices and internal function IRQ routing are:
+
+IRQ16 HPET IRQ
+IRQ17 HPET IRQ
+IRQ18 HPET IRQ
+IRQ19 HPET IRQ
+IRQ20 UHCI Port 0-1 IRQ and Card Boot IRQ
+IRQ21 EIDE IRQ and UHCI Port 4-5 IRQ
+IRQ22 UHCI Port 2-3 and SDIO
+IRQ23 Card Reader, EHCI Port 0-5
+
+HPET IRQs
+
+Mode Timer0 Timer1 Timer2
+--------------------------------------------
+Legacy 0(PIC)/2(APIC) 8(PIC)/8(APIC) -
+NonLeg 16-19 APIC 16-19 APIC 11,16-19 APIC
+
+
+ 83c 0a display IRQ 10
+603c 0a SDIO IRQ 10
+683c 09 card controller IRQ 9
+803c 0a UHCI 01 IRQ 10 INTA
+813c 09 UHCI 23 IRQ 9 INTB
+823c 0b UHCI 45 IRQ 11 INTC
+843c 0a EHCI IRQ 10 INTD
+a03c 09 HDAC IRQ 9
+
+[then]
Modified: cpu/x86/pc/apic.fth
===================================================================
--- cpu/x86/pc/apic.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/apic.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -1,9 +1,61 @@
-purpose: Advanced Programmable Interrupt Controller (APIC) driver
+purpose: Advanced Programmable Interrupt Controller driver
\ See license at end of file
+\ Docs:
+\ "Intel Architecture Software Developer's Manual", Volume 3, chapter 7.5:
+\ "Advanced Programmable Interrupt Controller (APIC)"
+\ See linux/include/asm-i386/i82489.h for further details.
+
+h# fee0.0000 constant apic-pa
+
+: apic-base-msr! ( l -- ) 0 h# 1b msr! ; \ High 32 bits are unused
+: apic-base-msr@ ( -- l ) h# 1b msr@ drop ;
+
+0 value apic-base \ Needs to be mapped and set
+
+: apic! ( l reg -- ) apic-base + l! ;
+: apic@ ( reg -- l ) apic-base + l! ;
+: apic-id! ( id -- ) d# 24 lshift d# 20 apic! ;
+: apic-id@ ( -- id ) d# 20 apic@ d# 24 rshift ;
+: apic-set ( mask reg -- ) dup apic@ rot or swap apic! ;
+: apic-clr ( mask reg -- ) dup apic@ rot invert and swap apic! ;
+: apic-lvt0-disable-irq ( -- ) h# 10000 h# 350 apic-set ; \ Disable LINT0
+: apic-lvt0-enable-irq ( -- ) h# 10000 h# 350 apic-clr ; \ Enable LINT0
+: apic-lvt1-disable-irq ( -- ) h# 10000 h# 360 apic-set ; \ Disable LINT1
+: apic-lvt1-enable-irq ( -- ) h# 10000 h# 360 apic-clr ; \ Enable LINT1
+: apic-timer! ( l -- ) h# 380 apic@ drop h# 380 apic! ;
+: apic-timer@ ( -- l ) h# 390 apic@ ;
+: apic-timer-disable-irq ( -- ) h# 10000 h# 320 apic-set ; \ Dis IRQ when timer passes 0
+: apic-timer-enable-irq ( -- ) h# 10000 h# 320 apic-clr ; \ Dis IRQ when timer passes 0
+: apic-timer-periodic ( -- ) h# 30000 h# 320 apic-set ;
+: apic-timer-one-shot ( -- ) h# 320 apic@ h# 20000 invert and h# 10000 or h# 320 apic! ;
+: apic-timer-irq! ( vector -- ) h# 320 apic@ h# ff invert and or h# 10000 or h# 320 apic! ;
+: apic-perf-disable-irq ( -- ) h# 10000 h# 340 apic-set ; \ Dis IRQ when perf timer passes 0
+: apic-perf-enable-irq ( -- ) h# 10000 h# 340 apic-clr ; \ Dis IRQ when perf timer passes 0
+: apic-perf-irq! ( vector -- ) h# 340 apic@ h# ff invert and or h# 10000 or h# 340 apic! ;
+: apic-on ( -- ) apic-base-msr@ h# fff and h# 800 or apic-pa or apic-base-msr! ;
+: apic-off ( -- ) apic-base-msr@ h# 800 invert and apic-base-msr! ;
+code cpu-capabilities ( -- n )
+ 1 # ax mov
+ cpuid
+ dx push
+c;
+: apic-present? ( -- flag ) cpu-capabilities h# 200 and 0<> ;
+: apic-soft-on ( -- )
+ h# f0 apic@
+ h# 100 or \ APIC on
+ h# 200 invert and \ Focus processor checking
+ h# ff or \ Spurious IRQ vector ff
+ h# f0 apic!
+;
+
+: apic-ack-irq ( -- ) h# f0 apic@ drop 0 h# b0 apic! ; \ b0 is eoi
+
+0 [if]
: apic@ ( index -- l ) h# fec0.0000 c! h# fec0.0010 l@ ;
: apic! ( l index -- ) h# fec0.0000 c! h# fec0.0010 l! ;
: apic-eoi ( vector -- ) h# fec0.0040 l! ;
+[then]
: .apic-mode ( low -- )
8 rshift 7 and case
@@ -42,27 +94,150 @@
pop-base
;
-\ LICENSE_BEGIN
-\ Copyright (c) 2007 FirmWorks
-\
-\ Permission is hereby granted, free of charge, to any person obtaining
-\ a copy of this software and associated documentation files (the
-\ "Software"), to deal in the Software without restriction, including
-\ without limitation the rights to use, copy, modify, merge, publish,
-\ distribute, sublicense, and/or sell copies of the Software, and to
-\ permit persons to whom the Software is furnished to do so, subject to
-\ the following conditions:
-\
-\ The above copyright notice and this permission notice shall be
-\ included in all copies or substantial portions of the Software.
-\
-\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
-\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-\
-\ LICENSE_END
+0 [if]
+\ For tdcr (3e0):
+\ Divisor: 1 2 4 8 16 32 64 128
+\ Value : b 0 1 2 3 8 9 a
+
+\ Timer base low bit at bit 18
+\ Timer base div is mask 2
+
+\ Other regs:
+\ LVR 0x30
+\ GET_APIC_VERSION(x) ((x)&0xFF)
+
+\ TPR 80 Task Priority, 000000xx only service interrupts higher than this value
+\ APR 90 Arbitration Priority, used during bus arbitration
+\ PPR a0 Processor Priority, depends complexly on TPR and incoming interrupt
+
+\ LDR 0xD0 Logical Destination Register II000000 II is logical APIC ID
+\ DFR 0xE0 Destination Format Register M0000000 M is the model (F:flat or 0:cluster)
+\ LVTERR 0x370
+\ TDCR 0x3E0
+\ ICR 0x310 Generate local interrupt by writing
+
+\ IRR 200 - 270 (8 registers - 256 bits) Request - bit is set if interrupt pending
+\ ISR 100 - 170 (8 registers - 256 bits) Service - INTA latches highest priority bit
+\ TMR 180 - 1F0 (8 registers - 256 bits) Bit is set for level, clear for edge. EOI commands sends EOI msg to all IOAPIC
+
+20 0
+30 50014
+80 f0
+d0 0
+e0 ffffffff
+f0 10f
+320 10000 Timer Masked off
+340 10000 PCINT Masked off
+350 700 LINT0 vector 0 mode ExtINT (111) Edge Trigger Active High
+360 400 LINT1 vector 0 mode NMI (100) Edge Trigger Active High
+370 10000 ERROR Masked off
+380 0
+390 0
+
+Io apic
+259 9 (def 08) bit 0=1 enabe MSI Flat Mode Support
+
+25c 10 APIC D11 is masked to 1, cluster mode disabled
+268-26f 0 .. 0 Priority of all CPUs = 0
+296 a - bit 0 = 0 Assert HDPWR# for both read / write cycles (other bits are enable V4 fast TRDY, dynamic HDPWR#)
+297 1 - bit 1 = 0 Don't pipeline APIC requests, bit 0 = 1 enable redirect low priority apic reqs to CPU 0
+386 3f - bit 5 ena apic low interrupt arb, bit 4 io apic fec80000 - fecf.ffff to PCI2, bit 3 host snoop, 2 enable top sm mem, 1 enable sdio support for using system memory 4kbytes, 1 enable compatible smm
+485 5 - bit 1 = 0 free-running apic clock (not dynamic) [Reserved in 855]
+488 0 - bits 1 and 0 free running apic clocks [Reserved in 855]
+4a2 d6 - bit 3 = 0 disable apic interface power management [Reserved in 855]
+
+-- Following registers in D0F5 are [Reserved in 855]
+540 4c (default) - bit 7 disable legacy apic, c is irrelevant if disabled
+541 0 (def) - irrelevant if 540 disabled
+542 3 (def) - bit 3 disable intx transparent mode, bit 2 dis apic nonshare mode, bit 1 ena APIC interrupt disable, bit 0 enabe boot interrupt function
+544 0 (def) - bit 7 boring, bit 1 dis pcie dev uses msi cycle wake up system from c3, bit 0 apic data voltage 2.5v
+-- End reserved
+
+
+io apic regs: fec0.0000
+00 index register for indirect regs
+10 data register for indirect regs
+20 write the IRQ #
+40 EOI WO
+
+indirect io apic regs
+00 1000000 IOAPIC ID is 1
+01 178003 (RO) version
+02 1000000 Arb ID is 1
+03 1 Front side bus message delivery
+10,11 0100.0000 . 0001.0000 DD00 . 0000 . 000 ooom . tips MVV
+..
+3e,3f 0100.0000 . 0001.0000
+ DD is destination APIC ID in physical mode (since bit 11 = 0)
+ m = 1 means masked
+
+
+8848 0 bit 7 = 0 address bit 2 of FSBis not force low (default)
+884d 1 bit 3=0 disable some funny thing about APCI Ch0 ext interrupt delivery (def), bit 2=0 dis ser irq always shared in APIC mode (def)
+
+PnP routing
+8854 00 non-inverted PCI INT#
+8855 a0 INTA IRQ10
+8856 b9 INTC IRQ11, INTB IRQ9
+8857 a0 INTD IRQ10
+
+APIC Mode INTA-H
+PIRQ16 A
+PIRQ17 B
+PIRQ18 C
+PIRQ19 D
+PIRQ20 E
+PIRQ21 F
+PIRQ22 G
+PIRQ23 H
+
+8858 60 (def 40) bit 6 ena Internal APIC
+885b 53 (def 01) bit 6 port 80 to LPC, bit 4 ena APIC clock gating, bit 3=0 dis bypass apic de-assert Msg, bit 1 res, bit 0 ena dynamic clock stop
+886c 00 (def) bit 3 dis apic positive decode
+88b0 30 (def 08) bits 5,4 ena uart 2,1, bit 3=0 disable apic C4P State Mode Control
+88e7 80 (def 00) bit 7 enable apic cycle reflect to all bus master activity effective signal
+88ec 00 (def 00) bits 7:4=0 disable V1 interrupt routing
+
+PMIO+65 bit 7 set to 1 to enable APIC interrupt wake up system from C4P state
+
+8f73 01 (def 00) bit4=0 enable APIC cycle block p2c write cycle (def), bit 0=1 enable pci broken master timer
+8f74 0c (def 00) bit3=1 lock cycle issued by cpu block p2c cycles, bit2=1 APIC FSB directly up through CCA (not PCI) and 7c[1] must also be set [Bit 2 is reserved in 855]
+8f7c 02 (def 02) bit2=1 APIC FSB directly up through CCA (not PCI) and 74[2] must also be set
+
+8f80 07 (def 00) bit0=1 APIC cycle blocks HDAC upstream write
+
+8fe0 93 (def 40) various. bit 3=0 dis APIC cycle flush HDAC Upstream Write Cycle [Reserved in 855]
+8fe6 3f (def 01) bit5 supposedly reserved, bit4=1 split fecxx.xxxx range btw PCI1 and PCI2, bit3=1 processor MSI support enable, bit2=1 Top SMM enable, bit1=1 High SMM enable, bit0=1 Compatible SMM enable
+
+
+
+When enable internal APIC, PCI devices and internal function IRQ routing are:
+
+IRQ16 HPET IRQ
+IRQ17 HPET IRQ
+IRQ18 HPET IRQ
+IRQ19 HPET IRQ
+IRQ20 UHCI Port 0-1 IRQ and Card Boot IRQ
+IRQ21 EIDE IRQ and UHCI Port 4-5 IRQ
+IRQ22 UHCI Port 2-3 and SDIO
+IRQ23 Card Reader, EHCI Port 0-5
+
+HPET IRQs
+
+Mode Timer0 Timer1 Timer2
+--------------------------------------------
+Legacy 0(PIC)/2(APIC) 8(PIC)/8(APIC) -
+NonLeg 16-19 APIC 16-19 APIC 11,16-19 APIC
+
+
+ 83c 0a display IRQ 10
+603c 0a SDIO IRQ 10
+683c 09 card controller IRQ 9
+803c 0a UHCI 01 IRQ 10 INTA
+813c 09 UHCI 23 IRQ 9 INTB
+823c 0b UHCI 45 IRQ 11 INTC
+843c 0a EHCI IRQ 10 INTD
+a03c 09 HDAC IRQ 9
+
+[then]
Modified: cpu/x86/pc/biosload/config.fth
===================================================================
--- cpu/x86/pc/biosload/config.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/biosload/config.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -1,27 +1,34 @@
\ See license at end of file
-purpose: Establish configuration definitions
+purpose: Configuration for loading from a USB key via Syslinux
\ --- The environment that "boots" OFW ---
\ - Image Format - Example Media - previous stage bootloader
-\ Load and run in VirtualBox (also works for other emulators)
-create virtualbox-loaded
+\ - (Syslinux) COM32 format - USB Key w/ FAT FS - Syslinux
+create syslinux-loaded
-\ create debug-startup
+create via-demo
+
+create debug-startup
+
+create virtual-mode
+create linux-support
\ create serial-console
+\ create use-usb-debug-port
+create pc
+
+\ create pseudo-nvram
create resident-packages
create addresses-assigned \ Don't reassign PCI addresses
\ create virtual-mode
-\ create use-root-isa
-create use-timestamp-counter
-create use-pci-isa
-create use-isa-ide
+create use-root-isa
+\ create use-isa-ide
create use-ega
create use-elf
-\ create use-ne2000
create use-watch-all
-create use-null-nvram
-\ create no-floppy-node
+\ create use-null-nvram
+create pseudo-nvram
+create no-floppy-node
fload ${BP}/cpu/x86/pc/biosload/addrs.fth
Modified: cpu/x86/pc/linux.fth
===================================================================
--- cpu/x86/pc/linux.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/linux.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -97,6 +97,17 @@
: set-parameters ( cmdline$ -- )
screen-info linux-params /screen-info move \ Ostensibly screen info
+ h# 40 +lp h# 14 erase \ apm_bios_info (APM BIOS info)
+ h# 54 +lp h# 0c erase \ pad2
+ h# 60 +lp h# 10 erase \ ist_info (Intel SpeedStep BIOS info)
+ h# 70 +lp h# 10 erase \ pad3
+ h# 80 +lp h# 10 erase \ hd0_info (obsolete)
+ h# 90 +lp h# 10 erase \ hd1_info (obsolete)
+ h# a0 +lp h# 10 erase \ sys_desc_table (from MCA - Microchannel)
+ h# b0 +lp h# 90 erase \ pad4
+ h# 140 +lp h# 80 erase \ edid_info
+ h# 1c0 +lp h# 20 erase \ efi_info
+
linux-memtop ( #bytes )
d# 1023 invert and d# 1024 / ( #kbytes )
d# 1024 - h# 002 +lp w! \ Kbytes of extended (not the 1st meg) memory
Modified: cpu/x86/pc/mmusetup.fth
===================================================================
--- cpu/x86/pc/mmusetup.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/mmusetup.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -5,11 +5,18 @@
\ established by initmmu.fth
[ifdef] total-ram
-: (memory?) ( adr -- flag ) total-ram u< ;
+: in-ram? ( adr -- flag ) total-ram u< ;
[else]
h# 8000.0000 value ram-boundary
-: (memory?) ( adr -- flag ) ram-boundary u< ;
+: in-ram? ( adr -- flag ) ram-boundary u< ;
[then]
+: (memory?) ( adr -- flag )
+ dup in-ram? if ( adr )
+ h# a0000 h# 100000 within 0= \ Don't cache the DOS Hole
+ else ( adr )
+ drop false
+ then
+;
' (memory?) is memory?
dev /mmu
Modified: cpu/x86/pc/olpc/versions.fth
===================================================================
--- cpu/x86/pc/olpc/versions.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/versions.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -2,7 +2,7 @@
\ The overall firmware revision
macro: FW_MAJOR E
-macro: FW_MINOR 41
+macro: FW_MINOR 41a
\ The EC microcode
macro: EC_VERSION e34
Modified: cpu/x86/pc/olpc/via/addrs.fth
===================================================================
--- cpu/x86/pc/olpc/via/addrs.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/via/addrs.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -50,7 +50,7 @@
h# fe01.b000 constant ehci-pci-base
h# fe02.4000 constant sd-pci-base
h# fe02.8000 constant camera-pci-base
-h# fec0.0000 constant ioapic-mmio-base
+h# fec0.0000 constant io-apic-mmio-base
h# fed0.0000 constant hpet-mmio-base
h# fed3.0000 constant spi-mmio-base
h# fed4.0000 constant wdt-mmio-base
Modified: cpu/x86/pc/olpc/via/config.fth
===================================================================
--- cpu/x86/pc/olpc/via/config.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/via/config.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -11,6 +11,8 @@
\ - OBMD format - ROM - direct boot from ROM
create rom-loaded
+create coreboot-loaded
+
create virtual-mode
create addresses-assigned \ Define if base addresses are already assigned
\ create serial-console \ Define to default to serial port for console
Modified: cpu/x86/pc/olpc/via/devices.fth
===================================================================
--- cpu/x86/pc/olpc/via/devices.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/via/devices.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -19,6 +19,7 @@
fload ${BP}/cpu/x86/acpitimer.fth
fload ${BP}/cpu/x86/pc/olpc/via/smbus.fth \ SMBUS driver
+fload ${BP}/cpu/x86/apic.fth \ APIC driver
stand-init: CPU node
d# 1,500,000,000 " VIA,C7"
@@ -33,7 +34,8 @@
warning @ warning off
: stand-init-io ( -- )
stand-init-io
- acpi-calibrate-tsc
+\ acpi-calibrate-tsc
+ d# 800 to us-factor d# 800000 to ms-factor
;
warning !
@@ -128,6 +130,7 @@
devalias d disk
devalias n nand
devalias sd /sd/disk
+devalias c /ide at 0/disk
[ifndef] demo-board
.( Removing ctlr-selftest from 8042 open !!!) cr
@@ -161,6 +164,8 @@
fload ${BP}/ofw/core/filecmds.fth \ File commands: dir, del, ren, etc.
fload ${BP}/cpu/x86/pc/olpc/cmos.fth \ CMOS RAM indices are 1f..ff , above RTC
+.( XXX Not clearing CMOS) cr
+patch noop init-bios-cmos stand-init
devalias nand /nandflash
devalias mtd /nandflash
Modified: cpu/x86/pc/olpc/via/fw.bth
===================================================================
--- cpu/x86/pc/olpc/via/fw.bth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/via/fw.bth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -383,6 +383,17 @@
\needs ramdisk " " d# 128 config-string ramdisk
" " ' boot-file set-config-string-default \ Let the boot script set the cmdline
+: upup
+ " u:\irdpup.gz" to ramdisk
+ " console=ttyS0,115200 ide=nodma pmedia=ataflash nosmp noacpi" to boot-file
+ " u:\vmlpup" to boot-device
+;
+: cpup
+ " c:\initrd.gz" to ramdisk
+ " console=ttyS0,115200 ide=nodma pmedia=ataflash nosmp noacpi" to boot-file
+ " c:\vmlinuz" to boot-device
+;
+
[ifdef] Later
: dimmer ( -- ) screen-ih if " dimmer" screen-ih $call-method then ;
: brighter ( -- ) screen-ih if " brighter" screen-ih $call-method then ;
Added: cpu/x86/pc/olpc/via/ioinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/ioinit.fth (rev 0)
+++ cpu/x86/pc/olpc/via/ioinit.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,241 @@
+\ Also from FinalSetting.c
+
+ 0 4 devfunc \ PM_table
+ a0 80 80 mreg \ Enable dynamic power management (coreboot for vx800 uses f0; 70 bits are reserved on vx855)
+ a1 e0 e0 mreg \ Dynamic power management for DRAM
+ a2 d6 d6 mreg \ Dynamic clock stop controls (coreboot for vx8000 uses ff fe; 29 bits are reserved on vx800)
+ a3 80 80 mreg \ Toggle reduction on
+ a5 81 81 mreg \ "Reserved"
+ end-table
+
+\ cache_as_ram_auto.c : enable_shadow_ram
+
+ 0 3 devfunc
+\ Initial DOS hole settings, so the firmware can set things up
+ 80 ff ff mreg \ Enable R/W memory access to Cxxxx bank
+ 81 ff ff mreg \ Enable R/W memory access to Dxxxx bank
+ 82 ff ff mreg \ Enable R/W memory access to Exxxx bank
+ 83 30 30 mreg \ Enable R/W memory access to Fxxxx bank (30), no memory hole (0c), SMM switching of Axxxx bank (03)
+
+\ Final DOS hole settings, after stuff has been copied in, for reference
+\ 80 ff 2a mreg \ CC000-CFFFF off, C0000-C7FFF RO
+\ 81 ff 00 mreg \ D0000-DFFFF off
+\ 82 ff aa mreg \ E0000-EFFFF RO
+\ 83 ff 20 mreg \ Enable R/W memory access to Fxxxx bank (20), no memory hole (0c), SMM switching of Axxxx bank (03)
+ end-table
+
+ 0 3 devfunc
+ 86 38 38 mreg \ SMM and APIC Decoding: enable APIC lowest int arb, IOAPIC split decode, MSI (SMM later)
+ end-table
+
+ \ Additional Power Management Setup not in coreboot
+ 0 2 devfunc
+ 76 08 08 mreg \ AGTL Power down buffers in S3
+ 92 ff 40 mreg \ ACPI IO Base address
+ end-table
+
+ 0 4 devfunc
+ 84 ff db mreg \ Dynamic clocks
+ 85 ff 05 mreg \ Dynamic clocks
+ 89 ff f8 mreg \ Dynamic clocks
+ 8b ff bf mreg \ Dynamic clocks
+ 8d ff 30 mreg \ Self-refresh in C3 and C4
+ 90 ff ff mreg \ Gate clocks
+ 91 ff ff mreg \ Gate clocks
+ 92 cc cc mreg \ Dynamic buffer control, power down comparators
+ a8 20 20 mreg \ Central traffic controller dynamic clock stop
+ end-table
+
+ \ Bus tuning
+ 0 5 devfunc
+ 54 8f 80 mreg \ SM request gets high priority, PCCA occupancy timer off
+ 55 0f 04 mreg \ PCCA P2C Promote Timer value 4
+ 59 0f 02 mreg \ IGFX Promote Timer value 2
+ 5f 0f 06 mreg \ IPI Promote Timer value 6
+ 64 20 00 mreg \ Upstream MSI doesn't flush queued P2C Write Data
+ 80 0b 08 mreg \ Upstream Request 1T earlier
+ 83 ff 81 mreg \ P2PW down arb timer timer 8, P2PR down arb timer timer 1
+ 84 7f 28 mreg \ Downstream arbitration Timeout timer for C2P
+ 85 c0 c0 mreg \ Abort P2P cycle to PCI1, CPU to PCI1 cycle blocks next C2P cycle
+ a3 01 01 mreg \ 01 res be like Phx
+ end-table
+
+ d# 12 0 devfunc \ SDIO tuning
+ 44 01 01 mreg \ Enable backdoor
+ 8b 05 01 mreg \ Do not report 1.8V support
+ 8c c3 03 mreg \ Falling edge trigger for Slots 1 and 2 data in high speed
+ 8e ff 7e mreg \ Delay host clock for Slots 1, 2, 3 by 4.8 nS
+ 8f 09 01 mreg \ Falling edge trigger on slot 3 output clock under high speed
+[ifdef] demo-board
+ 99 ff f9 mreg \ Two slots
+[else]
+ 99 ff fa mreg \ Three slots
+[then]
+ end-table
+
+ d# 15 0 devfunc \ EIDE tuning
+ 40 02 02 mreg \ Enable primary channel
+ 4a ff 5e mreg \ Drive1 timing
+ 4b ff 20 mreg \ Drive0 timing
+ 4c f0 60 mreg \ Address setup time
+ 52 df 0e mreg \ Ultra dma wait strobe timing
+ 53 df c6 mreg \ Ultra DMA mode control
+ c4 1d 18 mreg \ Config 1
+\ d4 ac 24 mreg \ Config 3
+ d4 bc 34 mreg \ Config 3 - 10 res be like Phx
+ end-table
+
+ \ USB Tuning
+ d# 16 0 devfunc \ UHCI Ports 0,1
+ 4a 02 02 mreg \ Enable Stop Bus Master Cycle if HALT Bit is Asserted
+ 4b 60 60 mreg \ Enable New UHCI Dynamic Scheme - 66MHz (40) & 33MHz (20)
+ c1 20 00 mreg \ Disable USB PIRQ
+ end-table
+
+ d# 16 1 devfunc \ UHCI Ports 2,3
+ 4a 02 02 mreg \ Enable Stop Bus Master Cycle if HALT Bit is Asserted
+ 4b 60 60 mreg \ Enable New UHCI Dynamic Scheme - 66MHz (40) & 33MHz (20)
+ c1 20 00 mreg \ Disable USB PIRQ
+ end-table
+
+ d# 16 2 devfunc \ UHCI Ports 4,5
+ 4a 02 02 mreg \ Enable Stop Bus Master Cycle if HALT Bit is Asserted
+ 4b 60 60 mreg \ Enable New UHCI Dynamic Scheme - 66MHz (40) & 33MHz (20)
+ c1 20 00 mreg \ Disable USB PIRQ
+ end-table
+
+ d# 16 4 devfunc \ EHCI
+ 42 40 40 mreg \ Enable Check PRESOF of ITDOUT Transaction during Fetching Data from DRAM
+ 43 c0 c0 mreg \ Enable Dynamic Clock Scheme - 66MHz (80) & 33MHz (40)
+ 48 20 00 mreg \ Disable DMA bursts
+ 4c 03 03 mreg \ Squelch detector fine tune - 01 is 112.5 mV
+ 4d 10 10 mreg \ 10 res be like Phx
+ 4e 03 03 mreg \ reserved bit - setting is appropriate for vx800 03 res be like Phx
+ 4f 10 10 mreg \ Enable Clear RUN Bit when EHCI_IDLE
+ 50 80 80 mreg \ Fetch one more QH before de-asserting Doorbell
+ 52 ff 11 mreg \ be like Phx
+ 53 ff 3f mreg \ be like Phx
+ 55 ff ff mreg \ Disconnect level fine tune - 575 mV for ports 0-3
+ 56 0f 0f mreg \ Disconnect level fine tune - 575 mV for ports 4-5
+ 5a ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 0,1
+ 5b ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 2,3
+ 5c 0f 00 mreg \ DPLL Track Speed 2, DPLL Lock Speed 2
+ 5d ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 4,5
+ 64 05 05 mreg \ Bump NULL-SOF valid time to 8 micro frames (04), Inhibit C4 state on USB 1.1 ISO activity (01)
+ end-table
+
+ d# 17 0 devfunc \ Bus control and power management
+ 40 44 44 mreg \ Enable I/O Recovery time (40), Enable ports 4d0/4d1 for edge/level setting (04)
+ 42 fc f0 mreg \ Various setting related to DMA line buffers
+ 43 0f 0b mreg \ Enable PCI delayed transactions (08), Write transaction timer (02), Read transaction timer (01)
+\ 4d 01 01 mreg \ Enable LPC TPM
+\ 4e 08 08 mreg \ Enable ports 74/75 for CMOS RAM access
+ 4e 18 18 mreg \ Enable ports 74/75 for CMOS RAM access - 10 res be like Phx
+\ 50 40 40 mreg \ Disable USB device mode
+ 50 c0 c0 mreg \ Disable USB device mode - 80 res be like Phx
+ 52 1b 19 mreg \ No wait state between SIRQ transactions (10), Enable SIRQ (08), SIRQ frame is 6 clocks (3>1)
+ 53 80 80 mreg \ Enable PC/PCI DMA
+ 55 ff a0 mreg \ INTA and External General interrupt routing - INTA:IRQ10
+ 56 ff b9 mreg \ INTB,C routing - INTC:IRQ11, INTB:IRQ9
+ 57 f0 a0 mreg \ INTD routing - INTD:IRQ10
+ 58 40 40 mreg \ Enable Internal APIC
+\ 5b 10 10 mreg \ Enable APIC Clock Gating
+ 5b 53 53 mreg \ Enable APIC Clock Gating - 43 res be like Phx
+ 68 80 80 mreg \ Enable HPETs
+ 69 ff 00 mreg \ HPET base low
+ 6a ff d0 mreg \ HPET base mid
+ 6b ff fe mreg \ HPET base high
+ 6e ff 18 mreg \ COMB not pos decoded but otherwise set to 2f8, COMA pos decoded at 3f8
+ 70 ff 06 mreg \ SVID backdoor
+ 71 ff 11 mreg \ SVID backdoor
+ 72 ff 37 mreg \ SVID backdoor
+ 73 ff 33 mreg \ SVID backdoor
+ 80 20 20 mreg \ Debounce power button
+ 81 08 08 mreg \ 32-bit ACPI timer
+\ 81 08 00 mreg \ 24-bit ACPI timer - why?
+ 84 ff da mreg \ IRQs 7,6,4,3,1 are primary wakeups
+ 85 ff 40 mreg \ IRQ 14 is primary wakeup
+ 8a 9f 1f mreg \ C-state auto switching with normal latencies
+[ifdef] demo-board
+ 8d 18 18 mreg \ fast clock as throttle timer tick, hold SMI# low until event status cleared (FIXME for OLPC)
+[else]
+ 8d 18 10 mreg \ fast clock as throttle timer tick, do not hold SMI# low
+[then]
+
+ 94 ff 68 mreg \ be like Phx
+ 95 ff c1 mreg \ be like Phx
+ 97 ff 80 mreg \ be like Phx
+
+ 9b ff 88 mreg \ 80 res be like Phx
+ 9f ff ad mreg \ be like Phx (slot 3 is Card Reader not SDIO)
+
+ b4 80 00 mreg \ No positive decoding for UART1 ???
+ b7 40 40 mreg \ 40 res be like Phx
+ b8 fc 80 mreg \ UART DMA Control Registers Base low (port is 4080)
+ b9 ff 40 mreg \ UART DMA Control Registers Base high
+ ba 77 44 mreg \ COM1 DMA Channel Selects - DMA0 for both Transmit and Receive
+ bc ff 00 mreg \ SPI MMIO Base Address 15:8 (address is fed30000)
+ bd ff d3 mreg \ SPI MMIO Base Address 23:16
+ be ff fe mreg \ SPI MMIO Base Address 31:24
+ d0 f0 00 mreg \ SMBUS IO Base Address low (port is 4100)
+ d1 ff 41 mreg \ SMBUS IO Base Address high
+ d2 0f 01 mreg \ Enable SMBUS and set other characteristics
+ e2 80 80 mreg \ Inhibit C4 during USB isochronous transaction
+ e4 ff a0 mreg \ Enable short C3/C4 (80), select various multi-function pins
+ e5 60 60 mreg \ Enable NM bus master as source of bus master status, enable NB int to wakeup from Cx
+ e6 20 20 mreg \ Enable USB Device Mode Bus Master as Break Event
+ e7 80 80 mreg \ Enable APIC Cycle Reflect to ALL Bus Master Activity Effective Signal
+ fc 06 04 mreg \ DPSLP# to SLP# Latency Adjustment - 22.5 us
+ end-table
+
+ d# 17 7 devfunc \ South-North Module Interface Control
+ 50 df 08 mreg \ SM priorities - HDAC high priority, others low
+ 51 80 80 mreg \ Enable subtractive decode for P2P cycle
+ 54 7b 02 mreg \ CCA REQ timing - synchronize USB REQ but not others
+0 [if]
+ 61 ff 2a mreg \ Page C ROM shadow - C0000-CBFFF RO, CC000-CFFFF off
+ 62 ff 00 mreg \ Page D ROM shadow - D0000-DFFFF off
+ 63 f3 a0 mreg \ Page E/F ROM shadow - E0000-EFFFF RO, F0000-FFFFF RO, no memory hole
+ 64 ff aa mreg \ Page E ROM shadow - E0000-EFFFF RO
+[then]
+ 70 fb 82 mreg \ CPU to PCI flow control - CPU to PCI posted write, Enable Delay Transaction
+ 72 af ee mreg \ Read caching and prefix - various knobs (40 bit is reserved)
+ 73 79 01 mreg \ Enable PCI broken master timer & various knobs
+\ 74 d8 08 mreg \ Lock Cycle Issued by CPU Blocks P2C Cycles (04 bit is reserved)
+ 74 dc 0c mreg \ Lock Cycle Issued by CPU Blocks P2C Cycles - 04 res be like Phx
+ 75 ff 0f mreg \ Use New grant mechanism for PCI arbitration, PCI Master Bus Timeout is 7x16 PCI clock
+ 76 fd 50 mreg \ Enable PCI parking, Grant to CPU after 2 PC master grants
+ 77 58 48 mreg \ PCI1 FIFO empty blocks CPU to PCI read, Read FIFO times out after 1 ms
+ 80 07 07 mreg \ PCI1 and HDAC upstream read does not pass write, APCI blocks upstream write
+\ 82 3e 20 mreg \ Monitor CCA and SDIO2
+ 82 3f 21 mreg \ Monitor CCA and SDIO2 - 01 res be like Phx
+\ e0 e0 80 mreg \ Dynamic CCA clock
+ e0 f3 93 mreg \ Dynamic CCA clock - 13 res be like Phx
+\ e2 1e 00 mreg \ Use dynamic clocks for Downstream Interface, PCI1, Downstream HDAC, Downstream SM Internal PCI device
+ e2 1f 00 mreg \ Use dynamic clocks for Downstream Interface, PCI1, Downstream HDAC, Downstream SM Internal PCI device 01 res be like Phx
+ e3 ff 5e mreg \ PCI1 dynamic clock, PCI clock on when GRANT# asserted, Enable P2CR data timeout at 7*8 PCI clocks
+\ e6 1f 1f mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved)
+ e6 1f 19 mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved)
+\ fc 40 40 mreg \ Enable CCA Read Clock When MTXCTL state machine is not idle
+ fc 48 48 mreg \ Enable CCA Read Clock When MTXCTL state machine is not idle - 08 res be like Phx
+ end-table
+
+ d# 20 0 devfunc
+ 41 01 01 mreg \ Dynamic clock for HDAC
+ end-table
+
+ \ APIC setup
+ 0 2 devfunc
+ 59 01 01 mreg \ MSI Flat model support
+ 5c 10 10 mreg \ Data bit 11 mask for MSI
+ 97 01 01 mreg \ Redirect lowest priority MSI requests to APIC 00
+ end-table
+
+ 0 3 devfunc
+ 86 38 38 mreg \ SMM and APIC Decoding: enable APIC lowest int arb, IOAPIC split decode, MSI (SMM later)
+ end-table
+
+ \ Low 2 bits of 86:
+ \ x1 to write to SMM shadow memory behind VGA
+ \ 00 to run - Axxxxx hits VGA in normal mode, hits shadow DRAM in SMM
+ \ 01 to access VGA when in SMM (data cycles only)
Modified: cpu/x86/pc/olpc/via/olpc.bth
===================================================================
--- cpu/x86/pc/olpc/via/olpc.bth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/via/olpc.bth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -3,6 +3,7 @@
command: &builder &this
in: ${BP}/cpu/x86/pc/olpc/via/build/ec.img
in: ${BP}/cpu/x86/pc/olpc/via/build/romreset.di
+in: ${BP}/cpu/x86/pc/olpc/via/build/romstart.di
in: ${BP}/cpu/x86/pc/olpc/via/build/resume.di
in: ${BP}/cpu/x86/pc/olpc/via/build/rmstart.img
in: ${BP}/cpu/x86/pc/olpc/via/build/paging.di
@@ -59,8 +60,11 @@
dropin-base rom-pa - pad-file
+[ifdef] coreboot-loaded
+ " romstart.di" $add-file
+[else]
" romreset.di" $add-file
-\ " romstart.di" $add-file
+[then]
[ifdef] Later
" resume.di" $add-file
@@ -82,6 +86,7 @@
" ${BP}/dev/usb2/device/storage/build/usbstorage.fc" " usbstorage" $add-deflated-dropin
\ " mrv8686.bin" " mrv8686.bin" $add-deflated-dropin
+ " ${BP}/dev/pci/build/pcibridg.fc" " class060400" $add-deflated-dropin
" ${BP}/dev/ide/build/leghier.fc" " class01018a" $add-deflated-dropin
" ${BP}/dev/mmc/sdhci/build/sdhci.fc" " class080501" $add-deflated-dropin
" ${BP}/dev/mmc/sdhci/build/sdmmc.fc" " sdmmc" $add-deflated-dropin
@@ -145,6 +150,10 @@
" ${BP}/cpu/x86/pc/olpc/via/build/nandblaster_tx.bin" " nb_tx" $add-deflated-dropin
[then]
+[ifdef] coreboot-loaded
+ /rom h# 10000 - pad-file \ coreboot init image must be in last FLASH block
+ " coreboot.img" $add-file
+[else]
/rom h# 400 - pad-file \ rmstart image must start 0x400 from end
" rmstart.img" $add-file
@@ -184,6 +193,7 @@
/rom h# 80 - ofd @ fseek
sipbuf /sipbuf ofd @ fputs
+[then]
ofd @ fclose
Modified: cpu/x86/pc/olpc/via/pcinode.fth
===================================================================
--- cpu/x86/pc/olpc/via/pcinode.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/via/pcinode.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -67,7 +67,7 @@
also forth definitions
: pci-probe-list ( -- adr len )
- " 1,c,f,10,13,14"
+ " 1,2,3,4,5,6,7,8,9,a,b,c,d,e,f,10,11,12,13,14"
;
\ " c,f" dup config-string pci-probe-list
@@ -85,6 +85,16 @@
h# 0000.8000 to first-io \ Avoid mappings established by BIOS
[then]
+: pirq@ ( n -- irq )
+ case
+ 0 of h# 8855 config-b@ 4 rshift endof
+ 1 of h# 8856 config-b@ h# f and endof
+ 2 of h# 8856 config-b@ 4 rshift endof
+ 3 of h# 8857 config-b@ 4 rshift endof
+ ( default ) 0 swap
+ endcase
+;
+
\ Determine the parent interrupt information (the "interrupt line" in PCI
\ parlance) from the child's "interrupt pin" and the child's address,
\ returning "int-line true" if the child's interrupt line register should
@@ -92,7 +102,18 @@
: assign-int-line ( phys.hi.func INTx -- irq true )
\ Reiterate the value that is already in the int line register,
\ which was placed there by lower level init code
- drop h# 3c + config-b@ true
+ drop case
+ h# 5800 of 1 pirq@ true exit endof \ USB device - PIRQB
+ h# 6000 of 0 pirq@ true exit endof \ SDIO - PIRQA
+ h# 6800 of 0 pirq@ true exit endof \ SDC - PIRQA
+ h# 7800 of 1 pirq@ true exit endof \ EIDE - PIRQB
+ h# 8000 of 0 pirq@ true exit endof \ UHCI01 - PIRQ A
+ h# 8100 of 1 pirq@ true exit endof \ UHCI23 - PIRQ B
+ h# 8200 of 2 pirq@ true exit endof \ UHCI45 - PIRQ C
+ h# 8400 of 3 pirq@ true exit endof \ EHCI - PIRQ D
+ h# a000 of 1 pirq@ true exit endof \ HDAudio - PIRQ B
+ ( default ) dup h# 3c + config-b@ true rot \ Reiterate previous setting
+ endcase
;
0 value interrupt-parent
Modified: cpu/x86/pc/olpc/via/rmstart.fth
===================================================================
--- cpu/x86/pc/olpc/via/rmstart.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/via/rmstart.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -98,11 +98,8 @@
16-bit
- \ PLL startup?
+ h# 01 port80
- \ Return to here after the reset
- h# 02 port80
-
\ Invalidate TLB
op: ax ax xor
op: ax cr3 mov
@@ -166,7 +163,6 @@
h# 0f port80
-ResetBase .x cr
op: ad: ResetBase h# 10 #) far jmp \ Jump to Forth startup
\ Pad the startup code so that the main entry point ends up at the
Modified: cpu/x86/pc/olpc/via/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/via/romreset.bth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/via/romreset.bth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -53,249 +53,53 @@
h# 10.0000 constant ramtest-start
h# 20.0000 constant ramtest-end
-create uart-debug-startup
-: devfunc ( dev func -- )
- h# 100 * swap h# 800 * or h# 8000.0000 or
- [ also assembler ]
- # ebp mov " masked-config-writes" evaluate #) call
- [ previous ]
-;
-: end-table 0 c, ;
+fload ${BP}/cpu/x86/pc/olpc/via/startmacros.fth \ Via-oriented startup macros
-: mreg ( reg# and or -- ) rot c, swap c, c, ;
-: wait-us ( us -- )
- " # ax mov usdelay #) call" evaluate
-;
-
-: showreg ( reg# -- )
- " h# ff port80 d# 200000 wait-us" eval
- " config-rb al 80 # out d# 1000000 wait-us" eval
-;
-
start-assembling
+hex
+
label my-entry
e9 c, 0 , \ To be patched later
end-code
-[ifdef] uart-debug-startup
-fload ${BP}/cpu/x86/pc/dot.fth \ Numeric output
-[then]
+fload ${BP}/cpu/x86/pc/romfind.fth \ find-dropin subroutine
-fload ${BP}/cpu/x86/pc/romfind.fth \ find-dropin
+fload ${BP}/cpu/x86/pc/olpc/via/startusdelay.fth \ microsecond delay subroutine
+fload ${BP}/cpu/x86/pc/olpc/via/startcfgio.fth \ masked config write subroutine
+fload ${BP}/cpu/x86/pc/olpc/via/startdraminit.fth \ DDRinit subroutine
-hex
-
-\ %ebp contains the config address
-\ %ebp used for merging config write data
-
-label masked-config-writes \ return address points to the table
- esi pop
- cld
- begin
- al lods \ al: register offset
- al al or 0<> while
- al bl mov \ bl: register offset
-
-[ifdef] config-to-port80
- h# 77 # al mov al h# 80 # out
- ebp eax mov ah al mov al h# 80 # out
- bl al mov al h# 80 # out
+[ifdef] debug-startup
+fload ${BP}/cpu/x86/pc/dot.fth \ Numeric output subroutine
+fload ${BP}/cpu/x86/pc/olpc/via/startcominit.fth \ cominit subroutine
[then]
- ebp eax mov \ Config address base
- bl al mov \ Merge in register number
- h# ffff.fffc # ax and \ Remove low bits
- h# cf8 # dx mov \ Config address register port #
- ax dx out \ Write to config address register
-
- 4 # dl add \ DX: cfc
- 3 # bl and \ Byte offset
- bl dl add \ Config data register port #
-
- al lods al not \ Get AND mask
- al al or 0<> if \ Do we need to read-modify-write?
- al ah mov \ Save mask
- dx al in \ Get existing value
-[ifdef] config-to-port80
- al h# 80 # out
-[then]
- ah al and \ Apply AND mask
- al ah mov
- al lods \ Get OR mask
- ah al or \ Now we have the final value
- else \ AND mask is 0 so we don't have to R-M-W
- al lods \ Get final value (== OR mask)
- then
-
-[ifdef] config-to-port80
- al h# 80 # out
-[then]
-
- al dx out \ Write final value to config data register
- repeat
- esi push
- ret
-end-code
-
-[ifdef] uart-debug-startup
-label cominit
- \ Turn on frame buffer
- 0 3 devfunc
- a1 ff 80 mreg \ Not sure why this is needed, the PM says it's the default
- a7 ff 08 mreg \ Internal GFX allocation
- end-table
-
- \ Turn on I/O and memory space access for display controller
- 1 0 devfunc
- 04 ff 07 mreg
- end-table
-
- 01 3c3 port-wb \ Graphics Chip IO port access on
- 10 3c4 port-wb 01 3c5 port-wb \ Graphics Chip register protection off
- 78 3c4 port-wb 86 3c5 port-wb \ South module pad share enable on (80)
-
- d# 17 0 devfunc
- \ The following is for UART on VCP port
- 46 3f 40 mreg
- \ The following is for UART on DVP port
- \ 46 3f c0 mreg
-
- \ Standard COM2 and COM1 IRQ routing
- b2 00 34 mreg
-
- \ For COM1 - 3f8 (ff below is 3f8 3 >> 80 or )
-
- b0 cf 10 mreg
- b4 00 ff mreg \ 3f8 3 >> 80 or - com base port
-
- \ For COM2 - 2f8 (df below is 2f8 3 >> 80 or )
- \ b0 cf 20 mreg
- \ b5 00 df mreg
- end-table
-
- \ The usual setup dance for a PC UART...
- 01 3fc port-wb \ DTR on
- 80 3fb port-wb \ Switch to bank 1 to program baud rate
- 01 3f8 port-wb \ Baud rate divisor low - 115200 baud
- 00 3f9 port-wb \ Baud rate divisor high - 115200 baud
- 03 3fb port-wb \ 8 bits, no parity, switch to bank 0
- 00 3f9 port-wb \ Interrupts off
- 00 3fa port-wb
-
- ret
-end-code
-[then]
-
-\ Delay N microseconds, N in ax
-label usdelay
- cx push
-
- ax cx mov
- begin h# 80 # al in loopa
-
- cx pop
- ret
-end-code
-
-\ This is the dance you have to do for each DDR rank to turn on the RAM chips
-label DDRinit
- 11 36b config-wb \ SDRAM NOP
- 0 #) ax mov \ Access RAM
- d# 200 wait-us
-
- 12 36b config-wb \ SDRAM Precharge All
- 0 #) ax mov \ Access RAM
-
- 13 36b config-wb \ SDRAM MRS Enable
- 20200 #) ax mov \ Access RAM for DLL enable - 150 ohm (20020 for 75 ohm)
- 800 #) ax mov \ Access RAM for DLL reset
-
- 12 36b config-wb \ SDRAM Precharge All
- 0 #) ax mov \ Access RAM
-
- 14 36b config-wb \ SDRAM CBR Cycle Enable
-
- 8 # cx mov
- begin
- 0 #) ax mov
- d# 100 wait-us
- loopa
-
- 13 36b config-wb \ SDRAM MRS Enable
- 101258 #) ax mov \ Depends on Twr, CL, and Burst Length
-
- 21e00 #) ax mov \ For 150 ohm; 75 ohm is 21c20
- 20200 #) ax mov \ For 150 ohm; 75 ohm is 21c20
-
- 10 36b config-wb \ SDRAM Normal
-
- ret
-end-code
-
-
label startup
-\ h# 10 port80
+ h# 10 port80
+
2 92 port-wb \ Enable A20
\ External A20GATE is disabled automatically because the internal KBC is on by default (cfg reg 8851 bit 0)
-\ Enable cache as RAM
- cr0 ax mov h# 4000.0000 bitset ax cr0 mov invd \ Disable cache
+ fload ${BP}/cpu/x86/pc/olpc/via/startcacheasram.fth
- 00000000.00000c00. 2ff set-msr \ Enable fixed and variable MTRRs in DefType
- 00000000.00000000. 250 set-msr \ Clear fixed MTRR
- 258 wmsr 259 wmsr 268 wmsr 269 wmsr 26a wmsr \ Fixed MTRRs
- 26b wmsr 26c wmsr 26d wmsr 26e wmsr 26f wmsr \ Fixed MTRRs
- 200 wmsr 201 wmsr 202 wmsr 203 wmsr 204 wmsr \ Variable MTRRs
- 205 wmsr 206 wmsr 207 wmsr 208 wmsr 209 wmsr \ Variable MTRRs
- 20a wmsr 20b wmsr 20c wmsr 20d wmsr 20e wmsr \ Variable MTRRs
- 20f wmsr \ Last variable one
+ \ We are now running from cache and can use the stack
- dcached-base 6 + 0 200 set-msr \ Dcache base address, write back
- /dcached negate h# 800 + f 201 set-msr \ Dcache size
- dropin-base 6 + 0 202 set-msr \ ROM base address
- /icached negate h# 800 + f 203 set-msr \ Icache size
-
- 00000000.00000800. 2ff set-msr \ Enable variable MTRRs in DefType
-
-
- cr0 ax mov h# 6000.0000 bitclr ax cr0 mov invd \ Cache on
-
- cld
-
- \ Access ROM to load it into the dcache
- dropin-base # esi mov
- /icached 4 / # ecx mov
- rep eax lods
-
- \ Access "RAM" area to load it into the dcache
- dcached-base # esi mov
- /dcached 4 / # ecx mov
- rep eax lods
-
- \ Put the stack pointer at the top of the dcached area
- dcached-base /dcached + 4 - # esp mov
- ds ax mov ax ss mov
-
-\ We are now running from cache, and can use the stack
-
-\ h# 20 port80 d# 300000 wait-us
-
\ cache_as_ram_auto.c: amd64_main()
01 004f config-wb \ Enable device 0 multiple functions
-\ 8898 config-rb al 80 # out d# 300000 wait-us
-
00 8898 config-wb \ Disable BIOS init timer GP3
-[ifdef] uart-debug-startup
- cominit #) call
- carret report
- linefeed report
+[ifdef] debug-startup
+ cominit #) call
[then]
+ carret report
+ linefeed report
+ char F report
+ h# 1d port80
+
\ This is a device ID backdoor to fake out the ID so Ubuntu will install
\ 8879 config-rb h# 40 # al or al dx out \ I don't know what this is, but coreboot does it
@@ -311,377 +115,29 @@
then
[then]
- \ enable_mainboard_devices()
-\ 41 8f4f config-wb \ Enable P2P Bridge Header for External PCI Bus (coreboot value)
- 43 8f4f config-wb \ As above, plus support extended PCIe config space
+ fload ${BP}/cpu/x86/pc/olpc/via/starthostctl.fth
+ fload ${BP}/cpu/x86/pc/olpc/via/demodram.fth
-\ 4f6 config-rb \ Get Northbridge revision ... don't need it because the
- \ init table contains no revision-specific entries
-
- \ via_pci_inittable(NBrevision,mNbStage1InitTbl)
-
- \ Enable extended config space for PCIe
- 0 5 devfunc \ NB_APIC
- 61 ff 0e mreg \ Set Exxxxxxx as PCIe MMIO config range
- 60 f4 13 mreg \ Support extended cfg address of PCIe (preserve 28 bits) (coreboot used vx800 bit resv in vx855)
- end-table
-
- 0 2 devfunc \ HOST CPU CTL
- 50 1f 08 mreg \ Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
- 51 ff 78 mreg \ CPU I/F Ctrl-1: Disable Fast DRDY and RAW (coreboot uses 7c)
- 52 cb cb mreg \ CPU I/F Ctrl-2: Enable all for performance
- 53 ff 44 mreg \ Arbitration: Host/Master Occupancy timer = 4*4 HCLK
- 54 1e 1c mreg \ Misc Ctrl: Enable 8QW burst Mem Access
-
- 55 06 04 mreg \ Miscellaneous Control 2
- 56 f7 63 mreg \ Write Policy 1
- 5d ff a2 mreg \ Write Policy
- 5e ff 88 mreg \ Bandwidth Timer
- 5f 46 46 mreg \ CPU Misc Ctrl
-
- 96 0b 0a mreg \ Write Policy
- 98 c1 41 mreg \ Bandwidth Timer
- 99 0e 06 mreg \ CPU Misc Ctrl
- 97 ff 00 mreg \ APIC Related Control
- end-table
-
-fload ${BP}/cpu/x86/pc/olpc/via/demodram.fth
-
- 0 3 devfunc
- 86 38 38 mreg \ SMM and APIC Decoding: enable APIC lowest int arb, IOAPIC split decode, MSI (SMM later)
- end-table
-
-
-\ Also from FinalSetting.c
-
- 0 4 devfunc \ PM_table
- a0 80 80 mreg \ Enable dynamic power management (coreboot for vx800 uses f0; 70 bits are reserved on vx855)
- a1 e0 e0 mreg \ Dynamic power management for DRAM
- a2 d6 d6 mreg \ Dynamic clock stop controls (coreboot for vx8000 uses ff fe; 29 bits are reserved on vx800)
- a3 80 80 mreg \ Toggle reduction on
- a5 81 81 mreg \ "Reserved"
- end-table
-
-\ UMARamSetting.c
-\ SetUMARam
- 0 3 devfunc
- a1 00 80 mreg \ Enable internal GFX
- a2 ff ee mreg \ Set GFX timers
- a4 ff 01 mreg \ GFX Data Delay to Sync with Clock
- a6 ff 76 mreg \ Page register life timer
- a7 ff 8c mreg \ Internal GFX allocation
- b3 ff 9a mreg \ Disable read past write
-\ de ff 06 mreg \ Enable CHA and CHB merge mode (but description says this value disable merging!) 00 for compatibility
- end-table
-
- 0 3 devfunc
- a1 70 40 mreg \ Set frame buffer size to 64M (8M:10, 16M:20, 32M:30, etc) - fbsize
- end-table
-
- 1 0 devfunc
- \ Reg 1b2 controls the number of writable bits in the BAR at 810
- b2 ff 70 mreg \ Offset of frame buffer, depends on size - fbsize
- 04 ff 07 mreg \ Enable IO and memory access to display
- end-table
-
- d000.0000 810 config-wl \ S.L. Base address
- f000.0000 814 config-wl \ MMIO Base address
- cd01 3a0 config-ww \ Set frame buffer size and CPU-relative address and enable
-
- 0 0 devfunc
- c6 02 02 mreg \ Enable MDA forwarding (not in coreboot)
- d4 00 03 mreg \ Enable MMIO and S.L. access in Host Control device
- fe 00 10 mreg \ 16-bit I/O port decoding for VGA (no aliases)
- end-table
-
- 1 0 devfunc
- b0 07 03 mreg \ VGA memory selection (coreboot uses 03, Phoenix 01. I think 03 is correct)
- end-table
-
- 01 3c3 port-wb \ Graphics chip IO port access on
- 10 3c4 port-wb 01 3c5 port-wb \ Turn off register protection
- 67 3c2 port-wb \ Enable CPU Display Memory access (2), use color not mono port (1)
-
- 68 3c4 port-wb e0 3c5 port-wb \ Size of System Local Frame Buffer - Value depends on frame buffer size - fbsize
- \ 00:512MB 80:256MB c0:128MB e0:64MB f0:32MB f8:16MB fc:8MB fe:4MB ff:2MB
-
- \ These 2 are scratch registers that communicate with the VGA BIOS
- 3d 3d4 port-wb 74 3d5 port-wb \ Value depends on DIMM frequency - used by VGA BIOS
- 39 3c4 port-wb 10 3c5 port-wb \ BIOS Reserved Register 0 - FBsize_MiB/4 - fbsize - VGA BIOS
-
- 5a 3c4 port-wb 01 3c5 port-wb \ Point to secondary registers
- 4c 3c4 port-wb 83 3c5 port-wb \ LCDCK Clock Synthesizer Value 2
- 5a 3c4 port-wb 00 3c5 port-wb \ Point back to primary registers
-
- 6d 3c4 port-wb e0 3c5 port-wb \ Base address [28:21] of SL in System Memory - base is 1c00.0000 - fbsize, memsize
- 6e 3c4 port-wb 00 3c5 port-wb \ Base address [36:29] of SL in System Memory
- 6f 3c4 port-wb 00 3c5 port-wb \ Base address [47:37] of SL in System Memory
-
- 36 3c4 port-wb 11 3c5 port-wb \ Subsystem Vendor ID 1
- 35 3c4 port-wb 06 3c5 port-wb \ Subsystem Vendor ID 0
- 38 3c4 port-wb 51 3c5 port-wb \ Subsystem ID 1
- 37 3c4 port-wb 22 3c5 port-wb \ Subsystem ID 0
-
- f3 3c4 port-wb 00 3c5 port-wb \ 1a for snapshot mode
- f3 3d4 port-wb 12 3c5 port-wb \ Snapshot mode control - 1a for snapshot mode
-
-\ cache_as_ram_auto.c : enable_shadow_ram
-
- 0 3 devfunc
-\ Initial DOS hole settings, so the firmware can set things up
- 80 ff ff mreg \ Enable R/W memory access to Cxxxx bank
- 81 ff ff mreg \ Enable R/W memory access to Dxxxx bank
- 82 ff ff mreg \ Enable R/W memory access to Exxxx bank
- 83 30 30 mreg \ Enable R/W memory access to Fxxxx bank (30), no memory hole (0c), SMM switching of Axxxx bank (03)
-
-\ Final DOS hole settings, after stuff has been copied in, for reference
-\ 80 ff 2a mreg \ CC000-CFFFF off, C0000-C7FFF RO
-\ 81 ff 00 mreg \ D0000-DFFFF off
-\ 82 ff aa mreg \ E0000-EFFFF RO
-\ 83 ff 20 mreg \ Enable R/W memory access to Fxxxx bank (20), no memory hole (0c), SMM switching of Axxxx bank (03)
- end-table
-
- \ Additional Power Management Setup not in coreboot
- 0 2 devfunc
- 76 08 08 mreg \ AGTL Power down buffers in S3
- 92 ff 40 mreg \ ACPI IO Base address
- end-table
-
- 0 4 devfunc
- 84 ff db mreg \ Dynamic clocks
- 85 ff 05 mreg \ Dynamic clocks
- 89 ff f8 mreg \ Dynamic clocks
- 8b ff bf mreg \ Dynamic clocks
- 8d ff 30 mreg \ Self-refresh in C3 and C4
- 90 ff ff mreg \ Gate clocks
- 91 ff ff mreg \ Gate clocks
- 92 cc cc mreg \ Dynamic buffer control, power down comparators
- a8 20 20 mreg \ Central traffic controller dynamic clock stop
- end-table
-
- \ Bus tuning
- 0 5 devfunc
- 54 8f 80 mreg \ SM request gets high priority, PCCA occupancy timer off
- 55 0f 04 mreg \ PCCA P2C Promote Timer value 4
- 59 0f 02 mreg \ IGFX Promote Timer value 2
- 5f 0f 06 mreg \ IPI Promote Timer value 6
- 64 20 00 mreg \ Upstream MSI doesn't flush queued P2C Write Data
- 80 0b 08 mreg \ Upstream Request 1T earlier
- 83 ff 81 mreg \ P2PW down arb timer timer 8, P2PR down arb timer timer 1
- 84 7f 28 mreg \ Downstream arbitration Timeout timer for C2P
- 85 c0 c0 mreg \ Abort P2P cycle to PCI1, CPU to PCI1 cycle blocks next C2P cycle
- end-table
-
- d# 12 0 devfunc \ SDIO tuning
- 44 01 01 mreg \ Enable backdoor
- 8b 05 01 mreg \ Do not report 1.8V support
- 8c c3 03 mreg \ Falling edge trigger for Slots 1 and 2 data in high speed
- 8e ff 7e mreg \ Delay host clock for Slots 1, 2, 3 by 4.8 nS
- 8f 09 01 mreg \ Falling edge trigger on slot 3 output clock under high speed
-[ifdef] demo-board
- 99 ff f9 mreg \ Two slots
-[else]
- 99 ff fa mreg \ Three slots
-[then]
- end-table
-
- d# 15 0 devfunc \ EIDE tuning
- 40 02 02 mreg \ Enable primary channel
- 4a ff 5e mreg \ Drive1 timing
- 4b ff 20 mreg \ Drive0 timing
- 4c f0 60 mreg \ Address setup time
- 52 df 0e mreg \ Ultra dma wait strobe timing
- 53 df c6 mreg \ Ultra DMA mode control
- c4 1d 18 mreg \ Config 1
- d4 ac 24 mreg \ Config 3
- end-table
-
- \ USB Tuning
- d# 16 0 devfunc \ UHCI Ports 0,1
- 4a 02 02 mreg \ Enable Stop Bus Master Cycle if HALT Bit is Asserted
- 4b 60 60 mreg \ Enable New UHCI Dynamic Scheme - 66MHz (40) & 33MHz (20)
- c1 20 00 mreg \ Disable USB PIRQ
- end-table
-
- d# 16 1 devfunc \ UHCI Ports 2,3
- 4a 02 02 mreg \ Enable Stop Bus Master Cycle if HALT Bit is Asserted
- 4b 60 60 mreg \ Enable New UHCI Dynamic Scheme - 66MHz (40) & 33MHz (20)
- c1 20 00 mreg \ Disable USB PIRQ
- end-table
-
- d# 16 2 devfunc \ UHCI Ports 4,5
- 4a 02 02 mreg \ Enable Stop Bus Master Cycle if HALT Bit is Asserted
- 4b 60 60 mreg \ Enable New UHCI Dynamic Scheme - 66MHz (40) & 33MHz (20)
- c1 20 00 mreg \ Disable USB PIRQ
- end-table
-
- d# 16 4 devfunc \ EHCI
- 42 40 40 mreg \ Enable Check PRESOF of ITDOUT Transaction during Fetching Data from DRAM
- 43 c0 c0 mreg \ Enable Dynamic Clock Scheme - 66MHz (80) & 33MHz (40)
- 48 20 00 mreg \ Disable DMA bursts
- 4c 03 03 mreg \ Squelch detector fine tune - 01 is 112.5 mV
-\ 4d 01 01 mreg \ reserved bit
-\ 4e 03 03 mreg \ reserved bit - setting is appropriate for vx800
- 4f 10 10 mreg \ Enable Clear RUN Bit when EHCI_IDLE
- 50 80 80 mreg \ Fetch one more QH before de-asserting Doorbell
- 55 ff ff mreg \ Disconnect level fine tune - 575 mV for ports 0-3
- 56 0f 0f mreg \ Disconnect level fine tune - 575 mV for ports 4-5
- 5a ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 0,1
- 5b ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 2,3
- 5c 0f 00 mreg \ DPLL Track Speed 2, DPLL Lock Speed 2
- 5d ff cc mreg \ HS termination resistor fine tune - 45 ohm, 48 ohm for ports 4,5
- 64 05 05 mreg \ Bump NULL-SOF valid time to 8 micro frames (04), Inhibit C4 state on USB 1.1 ISO activity (01)
- end-table
-
- d# 17 0 devfunc \ Bus control and power management
- 40 44 44 mreg \ Enable I/O Recovery time (40), Enable ports 4d0/4d1 for edge/level setting (04)
- 42 fc f0 mreg \ Various setting related to DMA line buffers
- 43 0f 0b mreg \ Enable PCI delayed transactions (08), Write transaction timer (02), Read transaction timer (01)
-\ 4d 01 01 mreg \ Enable LPC TPM
- 4e 08 08 mreg \ Enable ports 74/75 for CMOS RAM access
- 52 1b 19 mreg \ No wait state between SIRQ transactions (10), Enable SIRQ (08), SIRQ frame is 6 clocks (3>1)
- 53 80 80 mreg \ Enable PC/PCI DMA
- 55 ff a0 mreg \ INTA and External General interrupt routing - INTA:IRQ10
- 56 ff b9 mreg \ INTB,C routing - INTC:IRQ11, INTB:IRQ9
- 57 f0 a0 mreg \ INTD routing - INTD:IRQ10
- 58 40 40 mreg \ Enable Internal APIC
- 5b 10 10 mreg \ Enable APIC Clock Gating
- 68 80 80 mreg \ Enable HPETs
- 69 ff 00 mreg \ HPET base low
- 6a ff d0 mreg \ HPET base mid
- 6b ff fe mreg \ HPET base high
- 6e ff 18 mreg \ COMB not pos decoded but otherwise set to 2f8, COMA pos decoded at 3f8
- 70 ff 06 mreg \ SVID backdoor
- 71 ff 11 mreg \ SVID backdoor
- 72 ff 37 mreg \ SVID backdoor
- 73 ff 33 mreg \ SVID backdoor
- 80 20 20 mreg \ Debounce power button
-\ 81 08 00 mreg \ 24-bit ACPI timer - why?
- 84 ff da mreg \ IRQs 7,6,4,3,1 are primary wakeups
- 85 ff 40 mreg \ IRQ 14 is primary wakeup
- 8a 9f 1f mreg \ C-state auto switching with normal latencies
-[ifdef] demo-board
- 8d 18 18 mreg \ fast clock as throttle timer tick, hold SMI# low until event status cleared (FIXME for OLPC)
-[else]
- 8d 18 10 mreg \ fast clock as throttle timer tick, do not hold SMI# low
-[then]
-\ 9b 80 80 mreg \ reserved bit
- b4 80 00 mreg \ No positive decoding for UART1 ???
- b8 fc 80 mreg \ UART DMA Control Registers Base low (port is 4080)
- b9 ff 40 mreg \ UART DMA Control Registers Base high
- ba 77 44 mreg \ COM1 DMA Channel Selects - DMA0 for both Transmit and Receive
- bc ff 00 mreg \ SPI MMIO Base Address 15:8 (address is fed30000)
- bd ff d3 mreg \ SPI MMIO Base Address 23:16
- be ff fe mreg \ SPI MMIO Base Address 31:24
- d0 f0 00 mreg \ SMBUS IO Base Address low (port is 4100)
- d1 ff 41 mreg \ SMBUS IO Base Address high
- d2 0f 01 mreg \ Enable SMBUS and set other characteristics
- e2 80 80 mreg \ Inhibit C4 during USB isochronous transaction
- e4 ff a0 mreg \ Enable short C3/C4 (80), select various multi-function pins
- e5 60 60 mreg \ Enable NM bus master as source of bus master status, enable NB int to wakeup from Cx
- e6 20 20 mreg \ Enable USB Device Mode Bus Master as Break Event
- e7 80 80 mreg \ Enable APIC Cycle Reflect to ALL Bus Master Activity Effective Signal
- fc 06 04 mreg \ DPSLP# to SLP# Latency Adjustment - 22.5 us
- end-table
-
- d# 17 7 devfunc \ South-North Module Interface Control
- 50 df 08 mreg \ SM priorities - HDAC high priority, others low
- 51 80 80 mreg \ Enable subtractive decode for P2P cycle
- 54 7b 02 mreg \ CCA REQ timing - synchronize USB REQ but not others
-0 [if]
- 61 ff 2a mreg \ Page C ROM shadow - C0000-CBFFF RO, CC000-CFFFF off
- 62 ff 00 mreg \ Page D ROM shadow - D0000-DFFFF off
- 63 f3 a0 mreg \ Page E/F ROM shadow - E0000-EFFFF RO, F0000-FFFFF RO, no memory hole
- 64 ff aa mreg \ Page E ROM shadow - E0000-EFFFF RO
-[then]
- 70 fb 82 mreg \ CPU to PCI flow control - CPU to PCI posted write, Enable Delay Transaction
- 72 af ee mreg \ Read caching and prefix - various knobs (40 bit is reserved)
- 73 79 01 mreg \ Enable PCI broken master timer & various knobs
- 74 d8 08 mreg \ Lock Cycle Issued by CPU Blocks P2C Cycles (04 bit is reserved)
- 75 ff 0f mreg \ Use New grant mechanism for PCI arbitration, PCI Master Bus Timeout is 7x16 PCI clock
- 76 fd 50 mreg \ Enable PCI parking, Grant to CPU after 2 PC master grants
- 77 58 48 mreg \ PCI1 FIFO empty blocks CPU to PCI read, Read FIFO times out after 1 ms
- 80 07 07 mreg \ PCI1 and HDAC upstream read does not pass write, APCI blocks upstream write
- 82 3e 20 mreg \ Monitor CCA and SDIO2
- e0 e0 80 mreg \ Dynamic CCA clock
- e2 1e 00 mreg \ Use dynamic clocks for Downstream Interface, PCI1, Downstream HDAC, Downstream SM Internal PCI device
- e3 ff 5e mreg \ PCI1 dynamic clock, PCI clock on when GRANT# asserted, Enable P2CR data timeout at 7*8 PCI clocks
-\ e6 1f 1f mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved)
- e6 1f 19 mreg \ Split APIC decoding, Snoop FEEx.xxxx, Enable top SMM, High SMM, Compat SMM (20 bit is reserved)
- fc 40 40 mreg \ Enable CCA Read Clock When MTXCTL state machine is not idle
- end-table
-
- d# 20 0 devfunc
- 41 01 01 mreg \ Dynamic clock for HDAC
- end-table
-
- \ APIC setup
- 0 2 devfunc
- 59 01 01 mreg \ MSI Flat model support
- 5c 10 10 mreg \ Data bit 11 mask for MSI
- 97 01 01 mreg \ Redirect lowest priority MSI requests to APIC 00
- end-table
-
- 0 3 devfunc
- 86 38 38 mreg \ SMM and APIC Decoding: enable APIC lowest int arb, IOAPIC split decode, MSI (SMM later)
- end-table
-
- \ Low 2 bits of 86:
- \ x1 to write to SMM shadow memory behind VGA
- \ 00 to run - Axxxxx hits VGA in normal mode, hits shadow DRAM in SMM
- \ 01 to access VGA when in SMM (data cycles only)
-
- h# 1c00.0000 # mem-info-pa 4 + #) mov \ Top of memory
-
- long-offsets on
-
+ char o report
h# 1e port80
-\ Fix the MTRRs so the real RAM is cacheable, instead of the fake nonexistent area
- cr0 ax mov h# 6000.0000 bitset ax cr0 mov \ Cache off
-
- 0000.0000.0000.0c00. 2ff set-msr \ Enable fixed and variable MTRRs in DefType
+ fload ${BP}/cpu/x86/pc/olpc/via/startmtrrinit.fth
+ \ Cache is now setup normally, backed by memory
+ 'ebda # sp mov \ Move stack to real memory
- 0000.0000.0000.0006. 200 set-msr \ RAM starting at 0
- 0000.000f.c000.0800. 201 set-msr \ 1 GiB
- 0000.0000.ff00.0006. 202 set-msr \ ROM in last meg
- 0000.000f.ff00.0800. 203 set-msr \ 1 MiB
- 0000.0000.d000.0001. 204 set-msr \ Frame buffer - Write Combining mode
- 0000.000f.f000.0800. 205 set-msr \ 256 MB
+ fload ${BP}/cpu/x86/pc/olpc/via/startgfxinit.fth
+ fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth
- 0606.0606.0606.0606. 250 set-msr \ Cache 00000-7FFFF
- 0606.0606.0606.0606. 258 set-msr \ Cache 80000-9FFFF
- 0000.0000.0000.0000. 259 set-msr \ Don't Cache VGA range from A0000 to BFFFF
- 0606.0606.0606.0606. 268 set-msr \ Cache C0000-C7FFF
- 0606.0606.0606.0606. 269 set-msr \ Cache C8000-CFFFF
- 0606.0606.0606.0606. 26a set-msr \ Cache D0000-D7FFF
- 0606.0606.0606.0606. 26b set-msr \ Cache D8000-DFFFF
- 0606.0606.0606.0606. 26c set-msr \ Cache E0000-E7FFF
- 0606.0606.0606.0606. 26d set-msr \ Cache E8000-EFFFF
- 0606.0606.0606.0606. 26e set-msr \ Cache F0000-F7FFF
- 0606.0606.0606.0606. 26f set-msr \ Cache F8000-FFFFF
-
- cr0 ax mov h# 6000.0000 bitclr ax cr0 mov \ Cache on
- h# 10.0000 # sp mov \ Move stack to real memory
-
-\ Cache is now back on, with the final MTRR setup
-
- \ Now we can use the stack and do conventional subroutine calls
-
\ Enable the keyboard controller
\ 8851 config-rb 2 # ax or ax bx mov
\ 8851 config-setup bx ax mov al dx out \ Enable the keyboard configuration port
\ e2 2e port-wb 7 2f port-wb
-\ XXX need to set some registers in D17F7 "SNMIC" per chapter 21 of the BIOS Porting Guide
+ fload ${BP}/cpu/x86/pc/olpc/via/startmemtop.fth
h# 1f port80
-[ifdef] uart-debug-startup
- char F report
- char o report
- char r report
-[then]
+ char r report
fload ${BP}/cpu/x86/pc/resetend.fth
end-code
Added: cpu/x86/pc/olpc/via/romstart.bth
===================================================================
--- cpu/x86/pc/olpc/via/romstart.bth (rev 0)
+++ cpu/x86/pc/olpc/via/romstart.bth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,117 @@
+\ See license at end of file
+purpose: Build file for dropin dispatcher - version for direct ROM startup
+
+command: &builder &this
+build-now
+
+create debug-startup
+
+fload ${BP}/cpu/x86/pc/olpc/via/config.fth \ Address configuration
+
+
+\needs start-assembling fload ${BP}/cpu/x86/asmtools.fth
+\needs write-dropin fload ${BP}/forth/lib/mkdropin.fth
+
+fload ${BP}/cpu/x86/mmuparam.fth
+
+\ startmacros.fth defines some assembler macros that make MSR and I/O port
+\ access very easy by hiding the details of register use.
+
+fload ${BP}/cpu/x86/startmacros.fth
+fload ${BP}/cpu/x86/pc/port80.fth
+
+hex
+
+fload ${BP}/cpu/x86/pc/finddi.fth \ find-dropin and other tools
+
+fload ${BP}/cpu/x86/pc/olpc/via/startmacros.fth \ Via-oriented startup macros
+
+start-assembling
+
+label my-entry
+ e9 c, 0 , \ To be patched later
+end-code
+
+[ifdef] debug-startup
+fload ${BP}/cpu/x86/pc/dot.fth \ Numeric output
+[then]
+
+fload ${BP}/cpu/x86/pc/romfind.fth \ find-dropin
+
+hex
+
+fload ${BP}/cpu/x86/pc/olpc/via/startcfgio.fth \ masked config write subroutine
+
+[ifdef] debug-startup
+fload ${BP}/cpu/x86/pc/olpc/via/startcominit.fth \ cominit subroutine
+[then]
+
+label startup
+ 00 8898 config-wb \ Disable BIOS init timer GP3
+ 'ebda # sp mov \ Move stack to real memory
+
+[ifdef] debug-startup
+ cominit #) call
+[then]
+
+ carret report
+ linefeed report
+ char F report
+ h# 1d port80
+ char o report
+ h# 1e port80
+
+ fload ${BP}/cpu/x86/pc/olpc/via/startmtrrinit.fth
+ fload ${BP}/cpu/x86/pc/olpc/via/ioinit.fth
+
+1 [if]
+ 0 3 devfunc
+ 86 c4 84 mreg \ Enable top SMM memory (04) of size 4 MB (80 in c0 field)
+ end-table
+
+ d# 17 7 devfunc
+ e6 04 04 mreg \ Enable top SMM memory in North/South module
+ end-table
+[then]
+
+ fload ${BP}/cpu/x86/pc/olpc/via/startmemtop.fth
+
+ h# 1f port80
+ char r report
+
+ fload ${BP}/cpu/x86/pc/resetend.fth
+end-code
+
+also 386-assembler
+startup my-entry put-branch
+previous
+
+end-assembling
+
+writing romstart.di
+asm-base here over - 0 " start" write-dropin
+ofd @ fclose
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/startcacheasram.fth
===================================================================
--- cpu/x86/pc/olpc/via/startcacheasram.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startcacheasram.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,37 @@
+\ Enable cache as RAM
+ cr0 ax mov h# 4000.0000 bitset ax cr0 mov invd \ Disable cache
+
+ 00000000.00000c00. 2ff set-msr \ Enable fixed and variable MTRRs in DefType
+ 00000000.00000000. 250 set-msr \ Clear fixed MTRR
+ 258 wmsr 259 wmsr 268 wmsr 269 wmsr 26a wmsr \ Fixed MTRRs
+ 26b wmsr 26c wmsr 26d wmsr 26e wmsr 26f wmsr \ Fixed MTRRs
+ 200 wmsr 201 wmsr 202 wmsr 203 wmsr 204 wmsr \ Variable MTRRs
+ 205 wmsr 206 wmsr 207 wmsr 208 wmsr 209 wmsr \ Variable MTRRs
+ 20a wmsr 20b wmsr 20c wmsr 20d wmsr 20e wmsr \ Variable MTRRs
+ 20f wmsr \ Last variable one
+
+ dcached-base 6 + 0 200 set-msr \ Dcache base address, write back
+ /dcached negate h# 800 + f 201 set-msr \ Dcache size
+ dropin-base 6 + 0 202 set-msr \ ROM base address
+ /icached negate h# 800 + f 203 set-msr \ Icache size
+
+ 00000000.00000800. 2ff set-msr \ Enable variable MTRRs in DefType
+
+
+ cr0 ax mov h# 6000.0000 bitclr ax cr0 mov invd \ Cache on
+
+ cld
+
+ \ Access ROM to load it into the dcache
+ dropin-base # esi mov
+ /icached 4 / # ecx mov
+ rep eax lods
+
+ \ Access "RAM" area to load it into the dcache
+ dcached-base # esi mov
+ /dcached 4 / # ecx mov
+ rep eax lods
+
+ \ Put the stack pointer at the top of the dcached area
+ dcached-base /dcached + 4 - # esp mov
+ ds ax mov ax ss mov
Added: cpu/x86/pc/olpc/via/startcbgfxinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startcbgfxinit.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startcbgfxinit.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,37 @@
+ fb-pci-base 810 config-wl \ S.L. Base address
+ gfx-pci-base 814 config-wl \ MMIO Base address
+
+[ifdef] notdef
+ \ Determine the frame buffer size from the register that controls
+ \ the GFX base address register size bits
+ 8b2 config-rb \ Mask bits in al
+ h# 80 al or \ Insert high mask bit which isn't implemented
+ d# 24 # ax shl \ Move bits up so they can be sign-extended down
+ d# 2 # ax sar \ Shift into place with sign extension
+ ax not \ invert bitmask
+ ax inc \ Frame buffer size now in ax
+
+ \ Now convert it to the log2 of the size, starting at 4M
+ bx bx xor \ Initial value
+ h# 40.0000 # cx mov \ Test size
+ begin
+ cx ax test
+ 0= while
+ bx inc
+ 1 # cx shl \ Bump test size by a factor of 2
+ repeat
+
+ \ bx now contains the code that goes in bits 14:12 of D0F3 a0-a1
+
+ d# 12 # bx shl \ Move it into place
+ h# 8d01 # bx or \ Set GFX enable (8000), Framebuf enable (1), and Address (d000.0000 shifted)
+ h# 3a0 config-setup bx ax mov op: ax dx out \ Stuff it in the register
+[then]
+
+ h# 3a0 config-rw \ Get old value of config reg 3a0.w (D0F3 RxA0)
+ h# ffe invert # ax and \ Clear Frame Buffer Address bits
+ fb-pci-base d# 20 rshift # ax or \ Insert new value
+ ax bx mov
+ h# 3a0 config-setup bx ax mov op: ax dx out \ Stuff it in the register
+
+\ cd01 3a0 config-ww \ Set frame buffer size and CPU-relative address and enable
Added: cpu/x86/pc/olpc/via/startcfgio.fth
===================================================================
--- cpu/x86/pc/olpc/via/startcfgio.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startcfgio.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,81 @@
+purpose: Early-startup subroutine for masked PCI configuration writes
+
+\ masked-config-writes is a specialized subroutine that scans a
+\ compact in-line table of PCI configuration register entries.
+\ The characteristics of this table are optimized for setting up
+\ Via chipsets, in which the setup registers are in PCI configuration
+\ space. Each PCI device/function has numerous registers, so it
+\ is worthwhile to optimize for groups of writes to the same
+\ device/function.
+\
+\ Each entry is three bytes - register#, clear_mask, set_mask
+\ The register number is the low 8 bits of a PCI configuration
+\ register address. The high bits must already be in %ebp.
+\
+\ The calculation for each entry is:
+\ temp = read_config_byte(address);
+\ temp &= ~clear_mask;
+\ temp |= set_mask;
+\ write_config_byte(address, temp);
+\
+\ As an optimization, if clear_mask is 0, so that no bits would
+\ be cleared, the calculation reduces to:
+\ write_config_byte(address, set_mask);
+\
+\ The last table entry is denoted by a 0 register#.
+\ When the table has been completely processed, the subroutine
+\ returns to the address just after the table.
+\
+\ The table is created by macros defined in via/startmacros.fth
+
+\ %ebp contains the config address
+
+label masked-config-writes \ return address points to the table
+ esi pop
+ cld
+ begin
+ al lods \ al: register offset
+ al al or 0<> while
+ al bl mov \ bl: register offset
+
+[ifdef] config-to-port80
+ h# 77 # al mov al h# 80 # out
+ ebp eax mov ah al mov al h# 80 # out
+ bl al mov al h# 80 # out
+[then]
+
+ ebp eax mov \ Config address base
+ bl al mov \ Merge in register number
+ h# ffff.fffc # ax and \ Remove low bits
+ h# cf8 # dx mov \ Config address register port #
+ ax dx out \ Write to config address register
+
+ 4 # dl add \ DX: cfc
+ 3 # bl and \ Byte offset
+ bl dl add \ Config data register port #
+
+ al lods al not \ Get AND mask
+ al al or 0<> if \ Do we need to read-modify-write?
+ al ah mov \ Save mask
+ dx al in \ Get existing value
+[ifdef] config-to-port80
+ al h# 80 # out
+[then]
+ ah al and \ Apply AND mask
+ al ah mov
+ al lods \ Get OR mask
+ ah al or \ Now we have the final value
+ else \ AND mask is 0 so we don't have to R-M-W
+ al lods \ Get final value (== OR mask)
+ then
+
+[ifdef] config-to-port80
+ al h# 80 # out
+[then]
+
+ al dx out \ Write final value to config data register
+ repeat
+ esi push
+ ret
+end-code
+
Added: cpu/x86/pc/olpc/via/startcominit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startcominit.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startcominit.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,46 @@
+label cominit
+ \ Turn on frame buffer
+ 0 3 devfunc
+ a1 80 80 mreg \ This bit must be on so you can talk to the Graphics registers below
+ a7 08 08 mreg \ This one too
+ end-table
+
+ \ Turn on I/O space access for display controller
+ 1 0 devfunc
+ 04 01 01 mreg
+ end-table
+
+ 01 3c3 port-wb \ Graphics Chip IO port access on
+ 10 3c4 port-wb 01 3c5 port-wb \ Graphics Chip register protection off
+
+ \ The preceding setup was all so that we can write the following bit.
+ \ It seems silly to have a bit that controls the UART in the graphics
+ \ chip sequencer register block (additional editorializing elided...).
+
+ 78 3c4 port-wb 3c5 port-rb \ Old value in al
+ h# 80 # al or al bl mov \ Set south module pad share enable
+ 78 3c4 port-wb 3c5 # dx mov bl al mov al dx out
+
+ d# 17 0 devfunc
+ \ The following is for UART on VCP port
+ 46 c0 40 mreg
+ \ The following is for UART on DVP port
+ \ 46 c0 c0 mreg
+
+ \ Standard COM2 and COM1 IRQ routing
+ b2 ff 34 mreg
+
+ \ For COM1 - 3f8 (ff below is 3f8 3 >> 80 or )
+
+ b0 30 10 mreg
+ b4 ff ff mreg \ 3f8 3 >> 80 or - com base port
+
+ \ For COM2 - 2f8 (df below is 2f8 3 >> 80 or )
+ \ b0 30 20 mreg
+ \ b5 ff df mreg
+ end-table
+
+ init-com1 \ The usual setup dance for a PC UART...
+
+ ret
+end-code
Added: cpu/x86/pc/olpc/via/startdraminit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startdraminit.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startdraminit.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,34 @@
+\ This is the dance you have to do for each DDR rank to turn on the RAM chips
+label DDRinit
+ 11 36b config-wb \ SDRAM NOP
+ 0 #) ax mov \ Access RAM
+ d# 200 wait-us
+
+ 12 36b config-wb \ SDRAM Precharge All
+ 0 #) ax mov \ Access RAM
+
+ 13 36b config-wb \ SDRAM MRS Enable
+ 20200 #) ax mov \ Access RAM for DLL enable - 150 ohm (20020 for 75 ohm)
+ 800 #) ax mov \ Access RAM for DLL reset
+
+ 12 36b config-wb \ SDRAM Precharge All
+ 0 #) ax mov \ Access RAM
+
+ 14 36b config-wb \ SDRAM CBR Cycle Enable
+
+ 8 # cx mov
+ begin
+ 0 #) ax mov
+ d# 100 wait-us
+ loopa
+
+ 13 36b config-wb \ SDRAM MRS Enable
+ 101258 #) ax mov \ Depends on Twr, CL, and Burst Length
+
+ 21e00 #) ax mov \ For 150 ohm; 75 ohm is 21c20
+ 20200 #) ax mov \ For 150 ohm; 75 ohm is 21c20
+
+ 10 36b config-wb \ SDRAM Normal
+
+ ret
+end-code
Added: cpu/x86/pc/olpc/via/startgfxinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startgfxinit.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startgfxinit.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,63 @@
+\ UMARamSetting.c
+\ SetUMARam
+ 0 3 devfunc
+ 99 ff 73 mreg \ 61 res be like Phx
+ a1 00 80 mreg \ Enable internal GFX
+ a2 ff ee mreg \ Set GFX timers
+ a4 ff 01 mreg \ GFX Data Delay to Sync with Clock
+ a6 ff 76 mreg \ Page register life timer
+ a7 ff 8c mreg \ Internal GFX allocation
+ b3 ff 9a mreg \ Disable read past write
+\ de ff 06 mreg \ Enable CHA and CHB merge mode (but description says this value disable merging!) 00 for compatibility
+ end-table
+
+\ 0 3 devfunc
+\ a1 70 40 mreg \ Set frame buffer size to 64M (8M:10, 16M:20, 32M:30, etc) - fbsize
+\ end-table
+
+ 1 0 devfunc
+ \ Reg 1b2 controls the number of writable bits in the BAR at 810
+ b2 ff 70 mreg \ Offset of frame buffer, depends on size - fbsize
+ 04 ff 07 mreg \ Enable IO and memory access to display
+ end-table
+
+ d000.0000 810 config-wl \ S.L. Base address
+ f000.0000 814 config-wl \ MMIO Base address
+ cd01 3a0 config-ww \ Set frame buffer size and CPU-relative address and enable
+
+ 0 0 devfunc
+ c6 02 02 mreg \ Enable MDA forwarding (not in coreboot)
+ d4 00 03 mreg \ Enable MMIO and S.L. access in Host Control device
+ fe 00 10 mreg \ 16-bit I/O port decoding for VGA (no aliases)
+ end-table
+
+ 1 0 devfunc
+ b0 07 03 mreg \ VGA memory selection (coreboot uses 03, Phoenix 01. I think 03 is correct)
+ end-table
+
+ 01 3c3 port-wb \ Graphics chip IO port access on
+ 10 3c4 port-wb 01 3c5 port-wb \ Turn off register protection
+ 67 3c2 port-wb \ Enable CPU Display Memory access (2), use color not mono port (1)
+
+ 68 3c4 port-wb e0 3c5 port-wb \ Size of System Local Frame Buffer - Value depends on frame buffer size - fbsize
+ \ 00:512MB 80:256MB c0:128MB e0:64MB f0:32MB f8:16MB fc:8MB fe:4MB ff:2MB
+
+ \ These 2 are scratch registers that communicate with the VGA BIOS
+ 3d 3d4 port-wb 74 3d5 port-wb \ Value depends on DIMM frequency - used by VGA BIOS
+ 39 3c4 port-wb 10 3c5 port-wb \ BIOS Reserved Register 0 - FBsize_MiB/4 - fbsize - VGA BIOS
+
+ 5a 3c4 port-wb 01 3c5 port-wb \ Point to secondary registers
+ 4c 3c4 port-wb 83 3c5 port-wb \ LCDCK Clock Synthesizer Value 2
+ 5a 3c4 port-wb 00 3c5 port-wb \ Point back to primary registers
+
+ 6d 3c4 port-wb e0 3c5 port-wb \ Base address [28:21] of SL in System Memory - base is 1c00.0000 - fbsize, memsize
+ 6e 3c4 port-wb 00 3c5 port-wb \ Base address [36:29] of SL in System Memory
+ 6f 3c4 port-wb 00 3c5 port-wb \ Base address [47:37] of SL in System Memory
+
+ 36 3c4 port-wb 11 3c5 port-wb \ Subsystem Vendor ID 1
+ 35 3c4 port-wb 06 3c5 port-wb \ Subsystem Vendor ID 0
+ 38 3c4 port-wb 51 3c5 port-wb \ Subsystem ID 1
+ 37 3c4 port-wb 22 3c5 port-wb \ Subsystem ID 0
+
+ f3 3c4 port-wb 00 3c5 port-wb \ 1a for snapshot mode
+ f3 3d4 port-wb 12 3c5 port-wb \ Snapshot mode control - 1a for snapshot mode
Added: cpu/x86/pc/olpc/via/starthostctl.fth
===================================================================
--- cpu/x86/pc/olpc/via/starthostctl.fth (rev 0)
+++ cpu/x86/pc/olpc/via/starthostctl.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,34 @@
+ \ enable_mainboard_devices()
+\ 41 8f4f config-wb \ Enable P2P Bridge Header for External PCI Bus (coreboot value)
+\ 43 8f4f config-wb \ As above, plus support extended PCIe config space
+ 1 8f4f config-wb \ Disable P2P bridge
+
+\ 4f6 config-rb \ Get Northbridge revision ... don't need it because the
+ \ init table contains no revision-specific entries
+
+ \ via_pci_inittable(NBrevision,mNbStage1InitTbl)
+
+ \ Enable extended config space for PCIe
+ 0 5 devfunc \ NB_APIC
+ 61 ff 0e mreg \ Set Exxxxxxx as PCIe MMIO config range
+ 60 f4 13 mreg \ Support extended cfg address of PCIe (preserve 28 bits) (coreboot used vx800 bit resv in vx855)
+ end-table
+
+ 0 2 devfunc \ HOST CPU CTL
+ 50 1f 08 mreg \ Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
+ 51 ff 78 mreg \ CPU I/F Ctrl-1: Disable Fast DRDY and RAW (coreboot uses 7c)
+ 52 cb cb mreg \ CPU I/F Ctrl-2: Enable all for performance
+ 53 ff 44 mreg \ Arbitration: Host/Master Occupancy timer = 4*4 HCLK
+ 54 1e 1c mreg \ Misc Ctrl: Enable 8QW burst Mem Access
+
+ 55 06 04 mreg \ Miscellaneous Control 2
+ 56 f7 63 mreg \ Write Policy 1
+ 5d ff a2 mreg \ Write Policy
+ 5e ff 88 mreg \ Bandwidth Timer
+ 5f 46 46 mreg \ CPU Misc Ctrl
+
+ 96 0b 0a mreg \ Write Policy
+ 98 c1 41 mreg \ Bandwidth Timer
+ 99 0e 06 mreg \ CPU Misc Ctrl
+ 97 ff 00 mreg \ APIC Related Control
+ end-table
Added: cpu/x86/pc/olpc/via/startmacros.fth
===================================================================
--- cpu/x86/pc/olpc/via/startmacros.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startmacros.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,17 @@
+: devfunc ( dev func -- )
+ h# 100 * swap h# 800 * or h# 8000.0000 or
+ [ also assembler ]
+ # ebp mov " masked-config-writes" evaluate #) call
+ [ previous ]
+;
+: end-table 0 c, ;
+
+: mreg ( reg# and or -- ) rot c, swap c, c, ;
+: wait-us ( us -- )
+ " # ax mov usdelay #) call" evaluate
+;
+
+: showreg ( reg# -- )
+ " h# ff port80 d# 200000 wait-us" eval
+ " config-rb al 80 # out d# 1000000 wait-us" eval
+;
Added: cpu/x86/pc/olpc/via/startmemtop.fth
===================================================================
--- cpu/x86/pc/olpc/via/startmemtop.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startmemtop.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,21 @@
+ \ Determine the top of usable memory.
+ \ Start with the bottom address of the area used for the frame buffer.
+
+ bx bx xor
+ h# 6d h# 3c4 port-wb h# 3c5 port-rb al bl mov \ Sequencer register 6d
+ h# 6e h# 3c4 port-wb h# 3c5 port-rb al bh mov \ Sequencer register 6e
+ d# 21 # bx shl
+ \ There are some higher bits in 6f but we only support 32-bit addresses
+
+ \ Then subtract the top SMM memory size, if it is enabled
+ h# 386 config-rb
+ 4 # ax test 0<> if
+ 6 # ax shr \ Top SMM memory size field
+ ax cx mov \ Move to cx
+ h# 10.0000 # ax mov \ Field==0 means 1M
+ ax cl shl \ Now ax contains SMM memory size
+ ax bx sub \ Adjust bx
+ then
+
+ bx mem-info-pa 4 + #) mov \ Top of memory
+
Added: cpu/x86/pc/olpc/via/startmtrrinit.fth
===================================================================
--- cpu/x86/pc/olpc/via/startmtrrinit.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startmtrrinit.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,27 @@
+
+\ Fix the MTRRs so the real RAM is cacheable, instead of the fake nonexistent area
+ cr0 ax mov h# 6000.0000 bitset ax cr0 mov \ Cache off
+
+ 0000.0000.0000.0006. 200 set-msr \ RAM starting at 0
+ 0000.0000.0000.0c00. 2ff set-msr \ Enable fixed and variable MTRRs in DefType
+ 0000.000f.c000.0800. 201 set-msr \ 1 GiB
+ 0000.0000.ff00.0006. 202 set-msr \ ROM in last meg
+ 0000.000f.ff00.0800. 203 set-msr \ 1 MiB
+ 0000.0000.d000.0001. 204 set-msr \ Frame buffer - Write Combining mode
+ 0000.000f.f000.0800. 205 set-msr \ 256 MB
+
+ 0606.0606.0606.0606. 250 set-msr \ Cache 00000-7FFFF
+ 0606.0606.0606.0606. 258 set-msr \ Cache 80000-9FFFF
+ 0000.0000.0000.0000. 259 set-msr \ Don't Cache VGA range from A0000 to BFFFF
+ 0606.0606.0606.0606. 268 set-msr \ Cache C0000-C7FFF
+ 0606.0606.0606.0606. 269 set-msr \ Cache C8000-CFFFF
+ 0606.0606.0606.0606. 26a set-msr \ Cache D0000-D7FFF
+ 0606.0606.0606.0606. 26b set-msr \ Cache D8000-DFFFF
+ 0606.0606.0606.0606. 26c set-msr \ Cache E0000-E7FFF
+ 0606.0606.0606.0606. 26d set-msr \ Cache E8000-EFFFF
+ 0606.0606.0606.0606. 26e set-msr \ Cache F0000-F7FFF
+ 0606.0606.0606.0606. 26f set-msr \ Cache F8000-FFFFF
+
+ 0000.0000.0000.0c00. 2ff set-msr \ Enable fixed and variable MTRRs in DefType
+
+ cr0 ax mov h# 6000.0000 bitclr ax cr0 mov \ Cache on
Added: cpu/x86/pc/olpc/via/startusdelay.fth
===================================================================
--- cpu/x86/pc/olpc/via/startusdelay.fth (rev 0)
+++ cpu/x86/pc/olpc/via/startusdelay.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,10 @@
+\ Delay N microseconds, N in ax
+label usdelay
+ cx push
+
+ ax cx mov
+ begin h# 80 # al in loopa
+
+ cx pop
+ ret
+end-code
Modified: cpu/x86/pc/olpc/via/versions.fth
===================================================================
--- cpu/x86/pc/olpc/via/versions.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/olpc/via/versions.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -2,7 +2,7 @@
\ The overall firmware revision
macro: FW_MAJOR A
-macro: FW_MINOR 00
+macro: FW_MINOR 01
\ The EC microcode
macro: EC_VERSION e34
Modified: cpu/x86/pc/report.fth
===================================================================
--- cpu/x86/pc/report.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/report.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -11,6 +11,8 @@
h# 01 h# 3f8 isa-c! \ Baud rate divisor low - 115200 baud
h# 0 h# 3f9 isa-c! \ Baud rate divisor high - 115200 baud
h# 3 h# 3fb isa-c! \ 8 bits, no parity
+ h# 0 h# 3f9 isa-c! \ Interrupts off
+ h# 1 h# 3fa isa-c! \ Enable FIFO
;
\ Assembler macro to assemble code to send the character "char" to COM1
@@ -23,6 +25,7 @@
: init-com1 ( -- ) ;
: report ( char -- ) drop ;
[then]
+
\ LICENSE_BEGIN
\ Copyright (c) 2006 FirmWorks
\
Modified: cpu/x86/pc/resetend.fth
===================================================================
--- cpu/x86/pc/resetend.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ cpu/x86/pc/resetend.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -7,7 +7,7 @@
\ Beginning of "switch to new GDT" section
\ Move GDT to low memory. We use the first location at gdt-pa as
- \ the pointer, so you can't use description 0.
+ \ the pointer since 0 is an invalid descriptor number anyway.
gdt-pa # ax mov
0 [ax] sgdt \ Read GDT
2 [ax] si mov \ GDT base
Modified: dev/via/unichrome/loadpkg.fth
===================================================================
--- dev/via/unichrome/loadpkg.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ dev/via/unichrome/loadpkg.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -4,9 +4,20 @@
" display" device-name
fload ${BP}/dev/via/unichrome/pci.fth \ PCI interfaces
+defer idac@ \ Indexed DAC read
+defer idac! \ Indexed DAC write
+defer rmr@ \ Pixel read mask read
+defer rmr! \ Pixel read mask write
+defer plt@ \ Palette read
+defer plt! \ Palette write
+defer rindex! \ Read index for palette read
+defer windex! \ Write index for palatte write
+defer index! \ Index for generic IO
+defer video-on
+fload ${BP}/dev/video/controlr/vga.fth \ Standard VGA interfaces
fload ${BP}/dev/via/unichrome/unichrome.fth \ Controller code
\ fload ${BP}/dev/via/unichrome/accel2d.fth \ Accelerator
-\ fload ${BP}/dev/via/unichrome/gxvga.fth \ Text mode support
+fload ${BP}/dev/via/unichrome/vgamodes.fth \ Text mode support
fload ${BP}/dev/video/common/rectangle16.fth \ Rectangular graphics
fload ${BP}/cpu/x86/pc/olpc/expand16.fth \ Expand image by 2x
Modified: dev/via/unichrome/unichrome.fth
===================================================================
--- dev/via/unichrome/unichrome.fth 2009-05-06 18:54:58 UTC (rev 1174)
+++ dev/via/unichrome/unichrome.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -41,28 +41,28 @@
;
-\ VGA register access
+\ \ VGA register access
+\
+\ \ reset attribute address flip-flop
+\ : reset-attr-addr ( -- ) h# 3da ( input-status1 ) pc@ drop ;
+\
+\ : video-mode! ( b -- ) reset-attr-addr h# 03c0 pc! ;
+\ : attr! ( b index -- ) reset-attr-addr h# 03c0 pc! h# 03c0 pc! ;
+\ : attr@ ( index -- b )
+\ reset-attr-addr h# 03c0 pc! h# 03c1 pc@ reset-attr-addr
+\ ;
+\ : grf! ( b index -- ) h# 03ce pc! h# 03cf pc! ;
+\ : grf@ ( index -- b ) h# 03ce pc! h# 03cf pc@ ;
+\
+\ : crt@ ( index -- byte ) h# 3d4 pc! h# 3d5 pc@ ;
+\ : crt! ( byte index -- ) h# 3d4 pc! h# 3d5 pc! ;
+\
+\ : seq@ ( index -- byte ) h# 3c4 pc! h# 3c5 pc@ ;
+\ : seq! ( byte index -- ) h# 3c4 pc! h# 3c5 pc! ;
+\
+\ : misc@ ( -- byte ) h# 3cc pc@ ;
+\ : misc! ( byte -- ) h# 3c2 pc! ;
-\ reset attribute address flip-flop
-: reset-attr-addr ( -- ) h# 3da ( input-status1 ) pc@ drop ;
-
-: video-mode! ( b -- ) reset-attr-addr h# 03c0 pc! ;
-: attr! ( b index -- ) reset-attr-addr h# 03c0 pc! h# 03c0 pc! ;
-: attr@ ( index -- b )
- reset-attr-addr h# 03c0 pc! h# 03c1 pc@ reset-attr-addr
-;
-: grf! ( b index -- ) h# 03ce pc! h# 03cf pc! ;
-: grf@ ( index -- b ) h# 03ce pc! h# 03cf pc@ ;
-
-: crt@ ( index -- byte ) h# 3d4 pc! h# 3d5 pc@ ;
-: crt! ( byte index -- ) h# 3d4 pc! h# 3d5 pc! ;
-
-: seq@ ( index -- byte ) h# 3c4 pc! h# 3c5 pc@ ;
-: seq! ( byte index -- ) h# 3c4 pc! h# 3c5 pc! ;
-
-: misc@ ( -- byte ) h# 3cc pc@ ;
-: misc! ( byte -- ) h# 3c2 pc! ;
-
: pll, ( v44 v45 v46 misc -- ) bljoin l, ;
\ Timing table for various resolutions
@@ -88,7 +88,8 @@
\ width height htotal hsync hsyncend vtotal vsync vsyncend --pll-- misc
create mode3-table
- 640 w, 400 w, 800 w, 680 w, 776 w, 449 w, 412 w, 430 w, hex 35 04 05 67 pll, decimal
+\ 640 w, 400 w, 800 w, 680 w, 776 w, 449 w, 412 w, 430 w, hex 35 04 05 67 pll, decimal
+ 640 w, 400 w, 800 w, 680 w, 776 w, 449 w, 412 w, 430 w, hex 54 90 03 67 pll, decimal
\ width height htotal hsync hsyncend vtotal vsync vsyncend --pll-- misc
create mode12-table
@@ -99,7 +100,13 @@
: mode-3? ( -- flag ) res-entry mode3-table = ;
: mode-12? ( -- flag ) res-entry mode12-table = ;
-: find-timing-table ( width height -- error? )
+: find-timing-table ( width height depth -- error? )
+ \ Mode12 check
+ 4 = if 2drop mode12-table to res-entry false exit then ( width height )
+
+ \ Text mode 3 check
+ dup d# 400 = if 2drop mode3-table to res-entry false exit then ( width height )
+
res-table /res-table bounds ?do ( width height )
over i w@ = if ( width height )
dup i wa1+ w@ = if ( width height )
@@ -132,7 +139,10 @@
mode-12? if 8 + then
;
: hblankend ( -- n )
- mode-3? mode-12? or if d# 792 else htotal then
+\ mode-3? if d# 288 exit then
+ mode-3? if d# 792 exit then
+ mode-12? if d# 792 exit then
+ htotal
;
: vdisplay ( -- n ) height ;
: vblank ( -- n )
@@ -205,8 +215,9 @@
: seq-set ( mask reg# -- ) tuck seq@ or swap seq! ;
: seq-clr ( mask reg# -- ) tuck seq@ swap invert and swap seq! ;
-: crt-set ( mask reg# -- ) tuck crt@ or swap crt! ;
-: crt-clr ( mask reg# -- ) tuck crt@ swap invert and swap crt! ;
+\ : crt-set ( mask reg# -- ) tuck crt@ or swap crt! ;
+\ : crt-clr ( mask reg# -- ) tuck crt@ swap invert and swap crt! ;
+: crt-clr crt-clear ;
: pixels>bytes ( pixels -- bytes )
depth d# 24 = if d# 32 else depth then * 3 >> ( bytes )
@@ -237,17 +248,23 @@
: legacy-settings ( -- )
\ Some EGA legacy mode settings
03 00 seq! \ Release reset bits
- 01 01 seq! \ 8/9 timing (0 for mode 3)
- 0f 02 seq! \ Enable map planes 0 and 1 (3 for mode 3)
+ mode-3? if 00 else 01 then
+ 01 seq! \ 8/9 timing (0 for mode 3)
+ mode-3? if 03 else 0f then
+ 02 seq! \ Enable map planes 0 and 1 (3 for mode 3)
00 03 seq! \ Character map select
- 0e 04 seq! \ Extended memory present (2 for mode 3)
+ mode-3? if 02 else 0e then
+ 04 seq! \ Extended memory present (2 for mode 3)
0d 0a crt! \ Cursor start (text mode)
0e 0b crt! \ Cursor end (text mode)
00 0e crt! \ Cursor loc (text mode)
00 0f crt! \ Cursor loc (text mode)
- 10 11 crt! \ Refreshes per line, disable vertical interrupt (60 in mode 3, 70 in mode 12)
- 23 17 crt! \ address wrap, sequential access, not CGA compat mode (63 in mode 12)
+ mode-3? if 60 else mode-12? if 70 else 10 then then
+ 11 crt! \ Refreshes per line, disable vertical interrupt (60 in mode 3, 70 in mode 12)
+ mode-12? if 63 else 23 then
+ 17 crt! \ address wrap, sequential access, not CGA compat mode (63 in mode 12)
+
04 0e crt! \ Make the register dump match the snapshots
60 0f crt!
01 49 crt!
@@ -273,8 +290,10 @@
\ SRs set in romreset: 35-38,39,4c,68,6d-6f,78,f3
: tune-fifos ( -- )
- 20 3f 16 seq-mask \ FIFO threshold (VX855 value) (value is c in modes 3 and 12)
- 7f ff 17 seq-mask \ FIFO depth (VX855 value) (value is 1f in modes 3 and 12)
+ mode-3? mode-12? or if 0c else 20 then
+ 3f 16 seq-mask \ FIFO threshold (VX855 value) (value is c in modes 3 and 12)
+ mode-3? mode-12? or if 1f else 7f then
+ ff 17 seq-mask \ FIFO depth (VX855 value) (value is 1f in modes 3 and 12)
60 ff 18 seq-mask \ Display Arbiter (VX855 value)
18 21 seq! \ (typical request track FIFO number channel 0
@@ -323,17 +342,24 @@
dup c@ i grf! 1+
loop drop
+ \ For mode 3, add: 10 5 grf! 0e 6 grf! 0 7 grf!
+ mode-3? if
+ 10 5 grf!
+ 0e 6 grf!
+ 00 7 grf!
+ then
\ For mode 13, add: 40 5 grf!
-\ For mode 3, add: 10 5 grf! 0e 6 grf! 0 7 grf!
0 20 grf! 0 21 grf! 0 22 grf!
\ AT6 is 6 not 14, AT8-f is 8-f, not 38-3f (different intensities)
10 0 do i i attr! loop
- 01 10 attr! \ mode control (0c for text mode 3)
+ mode-3? if 0c else 01 then
+ 10 attr! \ mode control (0c for text mode 3)
00 11 attr! \ overscan color
0f 12 attr! \ color plane enable
- 00 13 attr! \ horizontal pixel pan - (08 for text mode 3)
+ mode-3? if 08 else 00 then
+ 13 attr! \ horizontal pixel pan - (08 for text mode 3)
00 14 attr! \ high bits of color palette index
htotal 3 >> 5 - dup 00 crt! 5 >> 08 36 crt-mask
@@ -359,10 +385,12 @@
ff 18 crt! 10 7 crt-set 40 9 crt-set 10 35 crt-set
\ HSYNC adjust
- 06 07 33 crt-mask \ 01 for text mode 3, 00 for mode 12
+ mode-3? if 01 else mode-12? if 00 else 06 then then
+ 07 33 crt-mask \ 01 for text mode 3, 00 for mode 12
\ Max scan line value 0
- 1f 9 crt-clr 1f 14 crt!
+ mode-3? if 0f else 00 then 1f 9 crt-mask
+ 1f 14 crt! \ Underline location
vblank 1- dup 15 crt! dup 5 >> 08 07 crt-mask dup 4 >> 20 09 crt-mask 7 >> 08 35 crt-mask
vblankend 1- 16 crt!
@@ -372,8 +400,13 @@
c8 33 crt-clr \ Gamma, interlace, prefetch, HSYNC shift
\ Offset
- width pixels>bytes to /scanline
- /scanline bytes>chunks dup 13 crt! 3 >> e0 35 crt-mask
+ mode-3? if
+ d# 40
+ else
+ width pixels>bytes to /scanline
+ /scanline bytes>chunks
+ then
+ dup 13 crt! 3 >> e0 35 crt-mask
\ fetch count
hdisplay pixels>bytes bytes>chunks 8 + dup 1 >> 1c seq! 9 >> 03 1d seq-mask
@@ -383,7 +416,7 @@
: set-primary-mode ( width height depth -- error? )
to depth to height to width
- width height find-timing-table ?dup if exit then
+ width height depth find-timing-table ?dup if exit then
80 17 crt-clr \ Assert reset
@@ -404,10 +437,10 @@
\ depth 8 <> set-gamma \ No gamma for 8bpp palette mode
false set-gamma
- \ Maybe do some power-up thingy here
- pll set-primary-dotclock
-
- use-ext-clock
+ mode-3? 0= if
+ pll set-primary-dotclock
+ use-ext-clock
+ then
\ 01 6b crt-clr \ Appears to be reserved RO bit
Added: dev/via/unichrome/vgamodes.fth
===================================================================
--- dev/via/unichrome/vgamodes.fth (rev 0)
+++ dev/via/unichrome/vgamodes.fth 2009-05-08 07:56:10 UTC (rev 1175)
@@ -0,0 +1,68 @@
+\ XXX get these from video/common/defer.fth
+\ false instance value 6-bit-primaries? \ Indicate if DAC only supports 6bpp
+\ defer ext-textmode ' noop to ext-textmode
+\ These are just to make vga.fth happy. They are ba
+\ defer rs@ defer rs!
+\ defer idac@ defer idac!
+\ defer xvideo-on
+\ From graphics.fth
+
+\ defer plt@
+\ defer plt!
+\ defer rindex!
+\ defer windex!
+
+: ext-textmode
+ use-vga-dac
+ h# ff h# e crt! h# ff h# f crt! \ Move the hardware cursor off-screen
+ h# 04 h# 33 crt! \ Hsync adjustment
+ h# 10 h# 35 crt! \ Clear extended bits that can't be on for this mode's size
+ h# 00 h# 15 seq! \ Not using graphics modes
+ h# 0c h# 16 seq! \ FIFO
+ h# 1f h# 17 seq! \ FIFO
+ h# 4e h# 18 seq! \ FIFO
+ h# 20 h# 1a seq! \ Extended mode memory access disable
+ h# 54 h# 1c seq! \ Hdisp fetch count low
+ h# 00 h# 1d seq! \ Hdisp fetch count high
+ h# 00 h# 51 seq! \ FIFO
+ h# 06 h# 58 seq! \ FIFO
+ h# 00 h# 71 seq! \ FIFO
+ h# 00 h# 73 seq! \ FIFO
+;
+\ defer rmr@ defer rmr!
+
+: (set-colors) ( adr index #indices -- )
+ swap windex!
+ 3 * bounds ?do i c@ plt! loop
+;
+
+\ fload ${BP}/dev/video/controlr/vga.fth
+fload ${BP}/dev/video/common/textmode.fth
+
+0 value pc-font-adr
+: (pc-font) ( -- fontparams )
+ pc-font-adr 0= if
+ " pcfont" " find-drop-in" evaluate if ( adr len )
+ drop to pc-font-adr
+ else
+ default-font exit
+ then
+ then
+
+ " /packages/terminal-emulator" find-package if ( phandle )
+ " decode-font" rot find-method if ( xt )
+ pc-font-adr swap execute ( font-params )
+ exit
+ then
+ then
+
+ \ Fallback
+ default-font
+;
+' (pc-font) to pc-font
+
+warning @ warning off
+: text-mode3 ( -- )
+ text-mode3
+;
+warning on
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