[OpenBIOS] L2 Cache Settings
segher at kernel.crashing.org
Sat Jan 27 02:00:35 CET 2018
On Fri, Jan 26, 2018 at 05:04:02AM -0500, Jd Lyons wrote:
> > On Jan 25, 2018, at 1:38 PM, Segher Boessenkool <segher at kernel.crashing.org> wrote:
> > On Thu, Jan 25, 2018 at 11:09:31AM -0500, Jd Lyons wrote:
> >> Segher, if you have some of the old White Papers on the CPU’s that shipped in Mac’s, or the upgrades offered by third parties, I’d like to get a look at them, if your not under NDA.
> > You can download this CPU documentation from NPX (who bought it from
> > FSL, and before it was Motorola). Those are good docs.
> Thanks, I did a few half hearted google searches, that didn’t yield the docs, I figured they we still around somewhere. Sometimes goole is obtuse, it’s like the computer from the Hitchhikers Guide, it matters how you ask the question.
(It probably does not help that is mistyped NXP).
7447a filetype:pdf is an easy way to find it (you want the "reference
> I wonder, in specific to emulating caches if that yields any performance increase.
Probably not. Your host's memory access do not get any faster, and the
increased bookkeeping will not help.
> 32 bit PPC is never going to get any faster,
Most (all?) 64-bit PowerPC cores can run 32-bit code just fine.
> With qemu-ppc I find the integer performance very well maintained, it seems to scale well with the host cpu, tho the FPU and the Vec units are woeful and need a lot of work.
The FPU can not be cheaply emulated at all on x86 (probably not on Arm
either, not sure). The most obvious thing that cannot be cheaply emulated
is fmadd (fused multiply add).
Some vector operations are hard to do, too (in addition to the float ones).
> It seems like it could be a challenge to emulate caches, I’ll have to dig deeper into qemu and see how the issue is dealt with.
Well, it probably should at least make the L2CR etc. registers work as
expected; they do not necessarily actually have to *do* anything, esp. not
if you only want to emulate the architectural state (so don't care about
for example emulating cache invalidate correctly where that is undefined
behaviour in the architecture, etc.)
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