[OpenBIOS] [PATCH] pci: add PCI bridge support for 32-bit PCI IO address spaces

[Mark Cave-Ayland]

Make sure that we set the upper 16-bits of the IO address for both the
PCI IO base and PCI IO limit registers.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland at ilande.co.uk>
---
 drivers/pci.c |    3 +++
 drivers/pci.h |    2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/pci.c b/drivers/pci.c
index 265ab0c..672dcd0 100644
--- a/drivers/pci.c
+++ b/drivers/pci.c
@@ -1494,6 +1494,7 @@ static void ob_configure_pci_bridge(pci_addr addr,
 
     /* Set the base limit registers */
     pci_config_write16(addr, PCI_MEMORY_BASE, ((*mem_base >> 16) & ~(0xf)));
+    pci_config_write16(addr, PCI_IO_BASE_UPPER, (*io_base >> 16));
     pci_config_write8(addr, PCI_IO_BASE, ((*io_base >> 8) & ~(0xf)));
 
     /* Always ensure legacy ioports are accessible during enumeration.
@@ -1501,6 +1502,7 @@ static void ob_configure_pci_bridge(pci_addr addr,
        the configuration process, so we allow them during the secondary
        bus scan and then set the correct IO limit below. */
     io_scan_limit = *io_base + (0xffff - *io_base);
+    pci_config_write16(addr, PCI_IO_LIMIT_UPPER, (io_scan_limit >> 16));
     pci_config_write8(addr, PCI_IO_LIMIT, (io_scan_limit >> 8) & ~(0xf));
 
     /* make pci bridge parent device, prepare for recursion */
@@ -1535,6 +1537,7 @@ static void ob_configure_pci_bridge(pci_addr addr,
 
     /* Set the limit registers */
     pci_config_write16(addr, PCI_MEMORY_LIMIT, (((*mem_base - 1) >> 16) & ~(0xf)));
+    pci_config_write16(addr, PCI_IO_LIMIT_UPPER, ((*io_base - 1) >> 16));
     pci_config_write8(addr, PCI_IO_LIMIT, (((*io_base - 1) >> 8) & ~(0xf)));
 
     /* Disable unused address spaces */
diff --git a/drivers/pci.h b/drivers/pci.h
index ea70e8a..883a531 100644
--- a/drivers/pci.h
+++ b/drivers/pci.h
@@ -47,7 +47,9 @@
 #define PCI_BASE_ADDR_5		0x24
 
 #define PCI_IO_BASE		0x1c
+#define PCI_IO_BASE_UPPER	0x30
 #define PCI_IO_LIMIT		0x1d
+#define PCI_IO_LIMIT_UPPER	0x32
 #define PCI_MEMORY_BASE		0x20
 #define PCI_MEMORY_LIMIT	0x22
 
-- 
1.7.10.4