[OpenBIOS] sun4u interrupt-map
tarl-b2 at tarl.net
Thu Apr 5 00:37:33 CEST 2012
On 2012-Apr-4 18:15 , Artyom Tarasenko wrote:
>> > Evidently on the Ultra-5, we aren't using three cells to identify the child,
>> > only two. So we probably skip child.mid in both of the above specifications.
> And what are child.hi and child.lo? Is it the physical address, stored
> in the reg property?
Yes. It's bus-binding specific. I don't remember what the parent bus of
the PCI node was on an Ultra-5, but presumably <3c,0> indicates the PCI
root complex. It should be from the reg property of that same PCI node.
> But then the filter (address& 0x3e) == 0x3c can potentially hit
> really a lot of devices?
In this case, the mask of 0x3e (0011.1110) presumably indicates there
are only five meaningful bits in the child address that should be used
for comparison. Interestingly, by having a zero in the intrspec field,
presumably it only allows one interrupt (zero) to be mapped in this case.
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