[OpenBIOS] [PATCH v3 3/3] ppc64: Re-enable SF bit after returning from ELF binary

[Andreas Färber]

v2:
* Don't set SF bit on entry.

Signed-off-by: Andreas Färber <andreas.faerber at web.de>
---
 arch/ppc/qemu/start.S        |    4 ++++
 include/arch/ppc/processor.h |    2 ++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/ppc/qemu/start.S b/arch/ppc/qemu/start.S
index 29cfc14..ab7240e 100644
--- a/arch/ppc/qemu/start.S
+++ b/arch/ppc/qemu/start.S
@@ -494,6 +494,10 @@ _GLOBAL(call_elf):
 	MTMSRD(r0)
 	blrl
 
+#ifdef CONFIG_PPC64
+    /* Restore SF bit */
+    LOAD_REG_IMMEDIATE(r0, MSR_SF | MSR_FP | MSR_ME | MSR_DR | MSR_IR)
+#endif
 	LOAD_REG_IMMEDIATE(r8, saved_stack)		// restore stack pointer
 	mr	r1,r8
 	PPC_LL r0, (STACKFRAME_MINSIZE + PPC_LR_STKOFF)(r1)
diff --git a/include/arch/ppc/processor.h b/include/arch/ppc/processor.h
index 21e4fab..e00fea0 100644
--- a/include/arch/ppc/processor.h
+++ b/include/arch/ppc/processor.h
@@ -40,6 +40,8 @@
 
 #ifndef MSR_VEC
 
+#define MSR_SF      (1<<63)     /* Sixty-Four Bit Mode */
+
 #define MSR_VEC		(1<<25)		/*  6: Enable AltiVec */
 #define MSR_POW		(1<<18)		/* 13: Enable Power Management */
 #define MSR_TGPR	(1<<17)		/* 14: TLB Update registers in use */
-- 
1.7.3.4