[OpenBIOS] r246 - in openbios-devel: arch/sparc32 include/sparc32 kernel

svn at openbios.org svn at openbios.org
Sat Nov 8 10:10:53 CET 2008


Author: blueswirl
Date: 2008-11-08 10:10:52 +0100 (Sat, 08 Nov 2008)
New Revision: 246

Added:
   openbios-devel/include/sparc32/asi.h
Removed:
   openbios-devel/arch/sparc32/asi.h
Modified:
   openbios-devel/arch/sparc32/entry.S
   openbios-devel/arch/sparc32/switch.S
   openbios-devel/arch/sparc32/vectors.S
   openbios-devel/kernel/bootstrap.c
Log:
Fix compilation on OpenBSD: avoid accidental system include file use

Deleted: openbios-devel/arch/sparc32/asi.h
===================================================================
--- openbios-devel/arch/sparc32/asi.h	2008-11-05 15:52:59 UTC (rev 245)
+++ openbios-devel/arch/sparc32/asi.h	2008-11-08 09:10:52 UTC (rev 246)
@@ -1,111 +0,0 @@
-/* $Id: asi.h,v 1.1 2002/07/12 17:06:36 zaitcev Exp $ */
-#ifndef _SPARC_ASI_H
-#define _SPARC_ASI_H
-
-/* asi.h:  Address Space Identifier values for the sparc.
- *
- * Copyright (C) 1995 David S. Miller (davem at caip.rutgers.edu)
- *
- * Pioneer work for sun4m: Paul Hatchman (paul at sfe.com.au)
- * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev at ipmce.su>
- */
-
-/* The first batch are for the sun4c. */
-
-#define ASI_NULL1           0x00
-#define ASI_NULL2           0x01
-
-/* sun4c and sun4 control registers and mmu/vac ops */
-#define ASI_CONTROL         0x02
-#define ASI_SEGMAP          0x03
-#define ASI_PTE             0x04
-#define ASI_HWFLUSHSEG      0x05
-#define ASI_HWFLUSHPAGE     0x06
-#define ASI_REGMAP          0x06
-#define ASI_HWFLUSHCONTEXT  0x07
-
-#define ASI_USERTXT         0x08
-#define ASI_KERNELTXT       0x09
-#define ASI_USERDATA        0x0a
-#define ASI_KERNELDATA      0x0b
-
-/* VAC Cache flushing on sun4c and sun4 */
-#define ASI_FLUSHSEG        0x0c
-#define ASI_FLUSHPG         0x0d
-#define ASI_FLUSHCTX        0x0e
-
-/* SPARCstation-5: only 6 bits are decoded. */
-/* wo = Write Only, rw = Read Write;        */
-/* ss = Single Size, as = All Sizes;        */
-#define ASI_M_RES00         0x00   /* Don't touch... */
-#define ASI_M_UNA01         0x01   /* Same here... */
-#define ASI_M_MXCC          0x02   /* Access to TI VIKING MXCC registers */
-#define ASI_M_FLUSH_PROBE   0x03   /* Reference MMU Flush/Probe; rw, ss */
-#define ASI_M_MMUREGS       0x04   /* MMU Registers; rw, ss */
-#define ASI_M_TLBDIAG       0x05   /* MMU TLB only Diagnostics */
-#define ASI_M_DIAGS         0x06   /* Reference MMU Diagnostics */
-#define ASI_M_IODIAG        0x07   /* MMU I/O TLB only Diagnostics */
-#define ASI_M_USERTXT       0x08   /* Same as ASI_USERTXT; rw, as */
-#define ASI_M_KERNELTXT     0x09   /* Same as ASI_KERNELTXT; rw, as */
-#define ASI_M_USERDATA      0x0A   /* Same as ASI_USERDATA; rw, as */
-#define ASI_M_KERNELDATA    0x0B   /* Same as ASI_KERNELDATA; rw, as */
-#define ASI_M_TXTC_TAG      0x0C   /* Instruction Cache Tag; rw, ss */
-#define ASI_M_TXTC_DATA     0x0D   /* Instruction Cache Data; rw, ss */
-#define ASI_M_DATAC_TAG     0x0E   /* Data Cache Tag; rw, ss */
-#define ASI_M_DATAC_DATA    0x0F   /* Data Cache Data; rw, ss */
-
-/* The following cache flushing ASIs work only with the 'sta'
- * instruction. Results are unpredictable for 'swap' and 'ldstuba',
- * so don't do it.
- */
-
-/* These ASI flushes affect external caches too. */
-#define ASI_M_FLUSH_PAGE    0x10   /* Flush I&D Cache Line (page); wo, ss */
-#define ASI_M_FLUSH_SEG     0x11   /* Flush I&D Cache Line (seg); wo, ss */
-#define ASI_M_FLUSH_REGION  0x12   /* Flush I&D Cache Line (region); wo, ss */
-#define ASI_M_FLUSH_CTX     0x13   /* Flush I&D Cache Line (context); wo, ss */
-#define ASI_M_FLUSH_USER    0x14   /* Flush I&D Cache Line (user); wo, ss */
-
-/* Block-copy operations are available only on certain V8 cpus. */
-#define ASI_M_BCOPY         0x17   /* Block copy */
-
-/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
-#define ASI_M_IFLUSH_PAGE   0x18   /* Flush I Cache Line (page); wo, ss */
-#define ASI_M_IFLUSH_SEG    0x19   /* Flush I Cache Line (seg); wo, ss */
-#define ASI_M_IFLUSH_REGION 0x1A   /* Flush I Cache Line (region); wo, ss */
-#define ASI_M_IFLUSH_CTX    0x1B   /* Flush I Cache Line (context); wo, ss */
-#define ASI_M_IFLUSH_USER   0x1C   /* Flush I Cache Line (user); wo, ss */
-
-/* Block-fill operations are available on certain V8 cpus */
-#define ASI_M_BFILL         0x1F
-
-/* This allows direct access to main memory, actually 0x20 to 0x2f are
- * the available ASI's for physical ram pass-through, but I don't have
- * any idea what the other ones do....
- */
-
-#define ASI_M_BYPASS       0x20   /* Reference MMU bypass; rw, as */
-#define ASI_M_FBMEM        0x29   /* Graphics card frame buffer access */
-#define ASI_M_VMEUS        0x2A   /* VME user 16-bit access */
-#define ASI_M_VMEPS        0x2B   /* VME priv 16-bit access */
-#define ASI_M_VMEUT        0x2C   /* VME user 32-bit access */
-#define ASI_M_VMEPT        0x2D   /* VME priv 32-bit access */
-#define ASI_M_SBUS         0x2E   /* Direct SBus access */
-#define ASI_M_CTL          0x2F   /* Control Space (ECC and MXCC are here) */
-
-
-/* This is ROSS HyperSparc only. */
-#define ASI_M_FLUSH_IWHOLE 0x31   /* Flush entire ICACHE; wo, ss */
-
-/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
-#define ASI_M_IC_FLCLEAR   0x36
-#define ASI_M_DC_FLCLEAR   0x37
-
-#define ASI_M_DCDR         0x39   /* Data Cache Diagnostics Register rw, ss */
-
-#define ASI_M_VIKING_TMP1  0x40	  /* Emulation temporary 1 on Viking */
-#define ASI_M_VIKING_TMP2  0x41	  /* Emulation temporary 2 on Viking */
-
-#define ASI_M_ACTION       0x4c   /* Breakpoint Action Register (GNU/Viking) */
-
-#endif /* _SPARC_ASI_H */

Modified: openbios-devel/arch/sparc32/entry.S
===================================================================
--- openbios-devel/arch/sparc32/entry.S	2008-11-05 15:52:59 UTC (rev 245)
+++ openbios-devel/arch/sparc32/entry.S	2008-11-08 09:10:52 UTC (rev 246)
@@ -8,7 +8,7 @@
  */
 
 #include "psr.h"
-#include "asi.h"
+#include "asm/asi.h"
 #include "asm/crs.h"
 #define __ASSEMBLY__
 #include "openbios/firmware_abi.h"

Modified: openbios-devel/arch/sparc32/switch.S
===================================================================
--- openbios-devel/arch/sparc32/switch.S	2008-11-05 15:52:59 UTC (rev 245)
+++ openbios-devel/arch/sparc32/switch.S	2008-11-08 09:10:52 UTC (rev 246)
@@ -1,5 +1,5 @@
 #include "psr.h"
-#include "asi.h"
+#include "asm/asi.h"
 #define ASI_BP ASI_M_BYPASS
 #define REGWIN_SZ   0x40
 

Modified: openbios-devel/arch/sparc32/vectors.S
===================================================================
--- openbios-devel/arch/sparc32/vectors.S	2008-11-05 15:52:59 UTC (rev 245)
+++ openbios-devel/arch/sparc32/vectors.S	2008-11-08 09:10:52 UTC (rev 246)
@@ -25,7 +25,7 @@
 
 #define __ASSEMBLY
 #include "psr.h"
-#include "asi.h"
+#include "asm/asi.h"
 #define SER_ADDR5  0x71100004
 #define SER_ADDR10 0xf1100004
 

Copied: openbios-devel/include/sparc32/asi.h (from rev 245, openbios-devel/arch/sparc32/asi.h)
===================================================================
--- openbios-devel/include/sparc32/asi.h	                        (rev 0)
+++ openbios-devel/include/sparc32/asi.h	2008-11-08 09:10:52 UTC (rev 246)
@@ -0,0 +1,111 @@
+/* $Id: asi.h,v 1.1 2002/07/12 17:06:36 zaitcev Exp $ */
+#ifndef _SPARC_ASI_H
+#define _SPARC_ASI_H
+
+/* asi.h:  Address Space Identifier values for the sparc.
+ *
+ * Copyright (C) 1995 David S. Miller (davem at caip.rutgers.edu)
+ *
+ * Pioneer work for sun4m: Paul Hatchman (paul at sfe.com.au)
+ * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev at ipmce.su>
+ */
+
+/* The first batch are for the sun4c. */
+
+#define ASI_NULL1           0x00
+#define ASI_NULL2           0x01
+
+/* sun4c and sun4 control registers and mmu/vac ops */
+#define ASI_CONTROL         0x02
+#define ASI_SEGMAP          0x03
+#define ASI_PTE             0x04
+#define ASI_HWFLUSHSEG      0x05
+#define ASI_HWFLUSHPAGE     0x06
+#define ASI_REGMAP          0x06
+#define ASI_HWFLUSHCONTEXT  0x07
+
+#define ASI_USERTXT         0x08
+#define ASI_KERNELTXT       0x09
+#define ASI_USERDATA        0x0a
+#define ASI_KERNELDATA      0x0b
+
+/* VAC Cache flushing on sun4c and sun4 */
+#define ASI_FLUSHSEG        0x0c
+#define ASI_FLUSHPG         0x0d
+#define ASI_FLUSHCTX        0x0e
+
+/* SPARCstation-5: only 6 bits are decoded. */
+/* wo = Write Only, rw = Read Write;        */
+/* ss = Single Size, as = All Sizes;        */
+#define ASI_M_RES00         0x00   /* Don't touch... */
+#define ASI_M_UNA01         0x01   /* Same here... */
+#define ASI_M_MXCC          0x02   /* Access to TI VIKING MXCC registers */
+#define ASI_M_FLUSH_PROBE   0x03   /* Reference MMU Flush/Probe; rw, ss */
+#define ASI_M_MMUREGS       0x04   /* MMU Registers; rw, ss */
+#define ASI_M_TLBDIAG       0x05   /* MMU TLB only Diagnostics */
+#define ASI_M_DIAGS         0x06   /* Reference MMU Diagnostics */
+#define ASI_M_IODIAG        0x07   /* MMU I/O TLB only Diagnostics */
+#define ASI_M_USERTXT       0x08   /* Same as ASI_USERTXT; rw, as */
+#define ASI_M_KERNELTXT     0x09   /* Same as ASI_KERNELTXT; rw, as */
+#define ASI_M_USERDATA      0x0A   /* Same as ASI_USERDATA; rw, as */
+#define ASI_M_KERNELDATA    0x0B   /* Same as ASI_KERNELDATA; rw, as */
+#define ASI_M_TXTC_TAG      0x0C   /* Instruction Cache Tag; rw, ss */
+#define ASI_M_TXTC_DATA     0x0D   /* Instruction Cache Data; rw, ss */
+#define ASI_M_DATAC_TAG     0x0E   /* Data Cache Tag; rw, ss */
+#define ASI_M_DATAC_DATA    0x0F   /* Data Cache Data; rw, ss */
+
+/* The following cache flushing ASIs work only with the 'sta'
+ * instruction. Results are unpredictable for 'swap' and 'ldstuba',
+ * so don't do it.
+ */
+
+/* These ASI flushes affect external caches too. */
+#define ASI_M_FLUSH_PAGE    0x10   /* Flush I&D Cache Line (page); wo, ss */
+#define ASI_M_FLUSH_SEG     0x11   /* Flush I&D Cache Line (seg); wo, ss */
+#define ASI_M_FLUSH_REGION  0x12   /* Flush I&D Cache Line (region); wo, ss */
+#define ASI_M_FLUSH_CTX     0x13   /* Flush I&D Cache Line (context); wo, ss */
+#define ASI_M_FLUSH_USER    0x14   /* Flush I&D Cache Line (user); wo, ss */
+
+/* Block-copy operations are available only on certain V8 cpus. */
+#define ASI_M_BCOPY         0x17   /* Block copy */
+
+/* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
+#define ASI_M_IFLUSH_PAGE   0x18   /* Flush I Cache Line (page); wo, ss */
+#define ASI_M_IFLUSH_SEG    0x19   /* Flush I Cache Line (seg); wo, ss */
+#define ASI_M_IFLUSH_REGION 0x1A   /* Flush I Cache Line (region); wo, ss */
+#define ASI_M_IFLUSH_CTX    0x1B   /* Flush I Cache Line (context); wo, ss */
+#define ASI_M_IFLUSH_USER   0x1C   /* Flush I Cache Line (user); wo, ss */
+
+/* Block-fill operations are available on certain V8 cpus */
+#define ASI_M_BFILL         0x1F
+
+/* This allows direct access to main memory, actually 0x20 to 0x2f are
+ * the available ASI's for physical ram pass-through, but I don't have
+ * any idea what the other ones do....
+ */
+
+#define ASI_M_BYPASS       0x20   /* Reference MMU bypass; rw, as */
+#define ASI_M_FBMEM        0x29   /* Graphics card frame buffer access */
+#define ASI_M_VMEUS        0x2A   /* VME user 16-bit access */
+#define ASI_M_VMEPS        0x2B   /* VME priv 16-bit access */
+#define ASI_M_VMEUT        0x2C   /* VME user 32-bit access */
+#define ASI_M_VMEPT        0x2D   /* VME priv 32-bit access */
+#define ASI_M_SBUS         0x2E   /* Direct SBus access */
+#define ASI_M_CTL          0x2F   /* Control Space (ECC and MXCC are here) */
+
+
+/* This is ROSS HyperSparc only. */
+#define ASI_M_FLUSH_IWHOLE 0x31   /* Flush entire ICACHE; wo, ss */
+
+/* Tsunami/Viking/TurboSparc i/d cache flash clear. */
+#define ASI_M_IC_FLCLEAR   0x36
+#define ASI_M_DC_FLCLEAR   0x37
+
+#define ASI_M_DCDR         0x39   /* Data Cache Diagnostics Register rw, ss */
+
+#define ASI_M_VIKING_TMP1  0x40	  /* Emulation temporary 1 on Viking */
+#define ASI_M_VIKING_TMP2  0x41	  /* Emulation temporary 2 on Viking */
+
+#define ASI_M_ACTION       0x4c   /* Breakpoint Action Register (GNU/Viking) */
+
+#endif /* _SPARC_ASI_H */

Modified: openbios-devel/kernel/bootstrap.c
===================================================================
--- openbios-devel/kernel/bootstrap.c	2008-11-05 15:52:59 UTC (rev 245)
+++ openbios-devel/kernel/bootstrap.c	2008-11-08 09:10:52 UTC (rev 246)
@@ -177,6 +177,9 @@
 		.relocation	= -1,
 		.length		= target_ulong(dicthead),
 		.last		= target_ucell(((unsigned long)last-(unsigned long)dict)),
+                .reserved[0]    = 0,
+                .reserved[1]    = 0,
+                .reserved[2]    = 0,
 	};
 
 	/*




More information about the OpenBIOS mailing list