[OpenBIOS] r488 - in cpu/ppc: . olpc olpc/build
svn at openbios.org
svn at openbios.org
Mon Jul 23 21:40:40 CEST 2007
Author: wmb
Date: 2007-07-23 21:40:40 +0200 (Mon, 23 Jul 2007)
New Revision: 488
Added:
cpu/ppc/cacheon.bth
cpu/ppc/cachinfl.bth
cpu/ppc/inflate.bth
cpu/ppc/olpc/olpc.bth
cpu/ppc/olpc/resetvec.bth
cpu/ppc/olpc/start.bth
Modified:
cpu/ppc/olpc/build/
cpu/ppc/olpc/devalias.fth
cpu/ppc/olpc/fw.bth
cpu/ppc/olpc/fwuboot.bth
cpu/ppc/olpc/pcinode.fth
cpu/ppc/ppcboot.fth
Log:
PowerPC OLPC build - Checkpoint.
Added: cpu/ppc/cacheon.bth
===================================================================
--- cpu/ppc/cacheon.bth (rev 0)
+++ cpu/ppc/cacheon.bth 2007-07-23 19:40:40 UTC (rev 488)
@@ -0,0 +1,55 @@
+purpose: Code to prepend to the inflater to run it with the cache on
+copyright: Copyright 1995 Firmworks All Rights Reserved
+
+command: &builder &this
+build-now
+
+fload ${BP}/cpu/ppc/asmtools.fth
+
+start-assembling
+
+\ This module use C calling and register usage conventions
+\ On entry,
+\ r1: C stack pointer
+\ r3: pointer to compressed image,
+\ r4: pointer to base of firmware RAM,
+\ r5: pointer to workspace area
+\ r6: size of firmware RAM
+
+label entry ( <as above> -- )
+ mfspr r0,lr \ C stack linkage and register saving
+ stw r31,-4(r1)
+ stw r0,8(r1)
+ stwu r1,h#-18(r1)
+
+ mfspr r31,hid0 \ r31: hid0
+
+ ori r0,r31,h#8800 \ Merge-in bits to invalidate and enable the Icache
+ sync isync
+ mtspr hid0,r0 \ Invalidate and enable Icache
+ isync sync
+
+ here 0 , \ Reserve space for a call instruction
+
+ sync isync
+ mtspr hid0,r31 \ Restore hid0 to its previous value
+ isync sync
+
+ addi r1,r1,h#18 \ C stack un-linkage and register restoration
+ lwz r0,8(r1)
+ mtspr lr,r0
+ lwz r31,-4(r1)
+
+ mtspr lr,r0 \ Return to caller
+ bclr 20,0
+
+here swap put-call \ Put a call to the following code in the place
+ \ that was reserved. The code to be called will
+ \ be concatenated to the end of this binary file.
+end-code
+
+end-assembling
+
+writing cacheon.img
+asm-base here over - ofd @ fputs
+ofd @ fclose
Added: cpu/ppc/cachinfl.bth
===================================================================
--- cpu/ppc/cachinfl.bth (rev 0)
+++ cpu/ppc/cachinfl.bth 2007-07-23 19:40:40 UTC (rev 488)
@@ -0,0 +1,36 @@
+purpose: Build script for the cacheon+inflater dropin
+copyright: Copyright 1997 FirmWorks All Rights Reserved
+
+command: &builder &this
+in: cacheon.img
+in: inflate.bin
+build-now
+
+\needs $add-dropin fload ${BP}/tools/mkdropin.fth
+
+\ Concatentate cacheon.img and inflate.bin and write it as a dropin file
+
+0 value bigbuf
+0 value /bigbuf
+
+: bufs+ ( adr1 len1 adr2 len2 -- adr3 len3 )
+ 2swap tuck ( adr2 len2 len1 adr1 len1 )
+ 3 pick + ( adr2 len2 len1 adr1 len3 )
+ tuck resize throw ( adr2 len2 len1 len3 adr3 )
+ tuck 2>r ( adr2 len2 len1 adr3 ) ( r: len3,adr3 )
+ + swap move ( ) ( r: len3,adr3 )
+ 2r> swap ( adr3 len3 )
+;
+
+
+" cachinfl.di" $new-file
+ " cacheon.img" $read-file ( adr1 len1 )
+ " inflate.bin" $read-file ( adr1 len1 adr2 len2 )
+
+ bufs+ ( adr3 len3 )
+
+ 2dup 0 " inflate" write-dropin ( adr3 len3 )
+
+ free-mem
+
+ofd @ fclose
Added: cpu/ppc/inflate.bth
===================================================================
--- cpu/ppc/inflate.bth (rev 0)
+++ cpu/ppc/inflate.bth 2007-07-23 19:40:40 UTC (rev 488)
@@ -0,0 +1,7 @@
+purpose: Build script for the inflater
+copyright: Copyright 1997 FirmWorks All Rights Reserved
+
+command: &builder &this
+build-now
+
+fload ${BP}/cpu/ppc/inflate.fth
Property changes on: cpu/ppc/olpc/build
___________________________________________________________________
Name: svn:ignore
- *.rom
ppcforth
+ *.rom
ppcforth
builton.fth
sourceurl
inflate.bin
Modified: cpu/ppc/olpc/devalias.fth
===================================================================
--- cpu/ppc/olpc/devalias.fth 2007-07-23 19:34:43 UTC (rev 487)
+++ cpu/ppc/olpc/devalias.fth 2007-07-23 19:40:40 UTC (rev 488)
@@ -1,20 +1,12 @@
purpose: Platform-specific device aliases
\ See license at end of file
-devalias net /pci/ethernet at e
+devalias net /pci/ethernet
+devalias disk /pci/disk
+devalias c /pci/disk
+devalias u /pci/usb/disk
+devalias com1 /serial
-.( XXX olpc/devalias.fth) cr
-devalias disk0 /pci/disk at 0,0:1
-devalias disk1 /pci/scsi at c/disk at 1,0:1
-devalias disk2 /pci/scsi at c/disk at 2,0:1
-devalias cdrom /pci/scsi at c/disk at 5,0
-
-devalias c /pci/scsi at c/disk at 0,0
-
-devalias disk /pci/scsi at c/disk at 0,0:1
-
-devalias com1 /serial at f1012000
-
\ LICENSE_BEGIN
\ Copyright (c) 2007 FirmWorks
\
Modified: cpu/ppc/olpc/fw.bth
===================================================================
--- cpu/ppc/olpc/fw.bth 2007-07-23 19:34:43 UTC (rev 487)
+++ cpu/ppc/olpc/fw.bth 2007-07-23 19:40:40 UTC (rev 488)
@@ -6,7 +6,6 @@
build-now
\ Configuration defines
-create bailout-early
true to stand-init-debug?
true constant real-mode?
@@ -100,7 +99,7 @@
h# 0200.0000 value fw-virt-size
headers
-0 value memsize
+h# 1000.0000 value memsize
fload ${BP}/cpu/ppc/loadvmem.fth \ /mmu node
stand-init: MMU
@@ -185,20 +184,15 @@
\ fload ${BP}/arch/prep/eagle.fth \ Eagle configuration registers
fload ${BP}/cpu/ppc/ppcboot.fth \ Forth startup code
-[ifdef] bailout-early
-: startup quit ;
+\ ---
-install-rom-cold
-
-.( --- Saving fw.dic ---) cr p" fw.dic" save-forth
-bye
-[then]
-
fload ${BP}/cpu/ppc/olpc/rootnode.fth \ Methods for root node
fload ${BP}/cpu/ppc/olpc/pcinode.fth \ System-specific words for PCI
-" " dup config-string pci-probe-list
+\ Don't probe 0; it is the host bridge thing and bad things
+\ happen if you change its BARs.
+" 7,8" dup config-string pci-probe-list
6 buffer: 'system-mac-address
: get-mac-address ( -- )
@@ -240,7 +234,7 @@
" /nvram" open-dev to nvram-node
init-config-vars
;
-[endif]
+[then]
\ fload ${BP}/dev/isa/irq.fth
@@ -254,26 +248,29 @@
fload ${BP}/cpu/ppc/olpc/devalias.fth \ Device aliases
-0 0 " fff00000" " /" begin-package
+0 0 " 0ff00000" " /" begin-package
" flash" device-name
- h# 8.0000 constant /device
+ h# 10.0000 dup constant /device
+ constant /device-phys
my-address my-space /device reg
fload ${BP}/cpu/x86/pc/flashpkg.fth
end-package
-devalias rom /flash at fff00000
+devalias rom /flash at 0ff00000
+[ifdef] notyet
fload ${BP}/cpu/ppc/olpc/flash.fth \ Low-level FLASH access
+[then]
-fload ${BP}/pkg/flash/saveflsh.fth \ FLASH to disk and back
-
\ ' false to interrupt-auto-boot? \ Don't do countdown
patch noop fw-title rom-cold \ Superseded by banner
+: startup quit ;
+
install-rom-cold
-.( --- Saving subset.dic ---) cr p" subset.dic" save-forth
+.( --- Saving fw.dic ---) cr p" fw.dic" save-forth
\ LICENSE_BEGIN
\ Copyright (c) 2007 FirmWorks
Modified: cpu/ppc/olpc/fwuboot.bth
===================================================================
--- cpu/ppc/olpc/fwuboot.bth 2007-07-23 19:34:43 UTC (rev 487)
+++ cpu/ppc/olpc/fwuboot.bth 2007-07-23 19:40:40 UTC (rev 488)
@@ -2,7 +2,7 @@
\ See license at end of file
command: &builder &this
-in: ${BP}/cpu/ppc/olpc/build/fw.dic
+in: ${BP}/cpu/ppc/olpc/build/olpc.img
build-now
create uboot-header
@@ -10,8 +10,8 @@
0 be-l, \ Header CRC, set later
0 be-l, \ Timestamp
0 be-l, \ Data size
- h# 0f000000 be-l, \ Load address
- h# 0f000000 be-l, \ Entry address
+ h# 0ff00000 be-l, \ Load address
+ h# 0ff00100 be-l, \ Entry address
0 be-l, \ Data CRC, set later
5 c, \ OS type - Linux
7 c, \ CPU type - PowerPC
@@ -26,7 +26,7 @@
fload ${BP}/forth/lib/crc32.fth
-reading fw.dic
+reading olpc.img
ifd @ fsize constant /image
/image buffer: filebuf
filebuf /image ifd @ fgets /image <> abort" Can't read image"
Added: cpu/ppc/olpc/olpc.bth
===================================================================
--- cpu/ppc/olpc/olpc.bth (rev 0)
+++ cpu/ppc/olpc/olpc.bth 2007-07-23 19:40:40 UTC (rev 488)
@@ -0,0 +1,65 @@
+purpose: Top-level build script for DDI DragonFly ROM
+copyright: Copyright 1997 FirmWorks All Rights Reserved
+
+command: &builder &this
+in: ${BP}/cpu/ppc/olpc/build/builton.fth
+in: ${BP}/cpu/ppc/olpc/build/resetvec.di
+in: ${BP}/cpu/ppc/olpc/build/cachinfl.di
+in: ${BP}/cpu/ppc/olpc/build/start.di
+in: ${BP}/cpu/ppc/olpc/build/fw.dic
+in: ${BP}/dev/mmc/sdhci/build/sdhci.fc
+in: ${BP}/dev/mmc/sdhci/build/sdmmc.fc
+in: ${BP}/dev/usb2/hcd/ohci/build/ohci.fc
+in: ${BP}/dev/usb2/hcd/ehci/build/ehci.fc
+in: ${BP}/dev/usb2/device/hub/build/hub.fc
+in: ${BP}/dev/usb2/device/net/build/usbnet.fc
+in: ${BP}/dev/usb2/device/serial/build/usbserial.fc
+in: ${BP}/dev/usb2/device/storage/build/usbstorage.fc
+in: ${BP}/dev/usb2/device/keyboard/build/usbkbd.fc
+in: ${BP}/dev/usb2/device/wlan/build/usb8388.fc
+in: ${BP}/dev/olpc/cafenand/build/cafenand.fc
+in: ${BP}/dev/olpc/cafecamera/build/cafecamera.fc
+in: ${BP}/dev/pci/build/pcibridg.fc
+\ in: ${BP}/dev/ide/build/idehier.fc
+\ in: usb8388.bin
+build-now
+
+\ Always re-create the builton.fth file when we make a new rom.img
+fload ${BP}/cpu/x86/pc/builton.bth
+\ fload ${BP}/cpu/x86/pc/olpc/sourceurl.fth
+
+writing olpc.img
+ " resetvec.di" $add-file
+ " start.di" $add-file
+ " cachinfl.di" $add-file
+
+\ " fw.dic" " firmware" $add-deflated-dropin
+ " fw.dic" " firmware" $add-dropin
+
+ " builton.fth" " probe-" $add-dropin
+\ " help.img" " help" $add-deflated-dropin
+
+ " ${BP}/dev/pci/build/pcibridg.fc" " class060400" $add-deflated-dropin
+\ " ${BP}/dev/ide/build/idehier.fc" " pci-ide" $add-deflated-dropin
+
+ " ${BP}/dev/usb2/hcd/ohci/build/ohci.fc" " class0c0310" $add-dropin
+ " ${BP}/dev/usb2/hcd/ehci/build/ehci.fc" " class0c0320" $add-dropin
+ " ${BP}/dev/usb2/device/hub/build/hub.fc" " usb,class9" $add-dropin
+ " ${BP}/dev/usb2/device/net/build/usbnet.fc" " usbnet" $add-dropin
+ " ${BP}/dev/usb2/device/keyboard/build/usbkbd.fc" " usb,class3" $add-dropin
+ " ${BP}/dev/usb2/device/serial/build/usbserial.fc" " usbserial" $add-dropin
+ " ${BP}/dev/usb2/device/storage/build/usbstorage.fc" " usbstorage" $add-dropin
+\ " ${BP}/dev/usb2/device/wlan/build/usb8388.fc" " usb1286,2001" $add-deflated-dropin
+\ " usb8388.bin" " usb8388.bin" $add-deflated-dropin
+
+ \ XXX the PCI device IDs should be different for the different CaFe functions
+ " ${BP}/dev/olpc/cafenand/build/cafenand.fc" " class050101" $add-dropin
+ " ${BP}/dev/olpc/cafecamera/build/cafecamera.fc" " pci11ab,4102" $add-dropin
+
+ " ${BP}/dev/mmc/sdhci/build/sdhci.fc" " pci11ab,4101" $add-dropin
+ " ${BP}/dev/mmc/sdhci/build/sdmmc.fc" " sdmmc" $add-dropin
+ " ${BP}/dev/geode/nandflash/build/nandflash.fc" " nand5536" $add-dropin
+
+ " ${BP}/ofw/inet/telnetd.fth" " telnetd" $add-deflated-dropin
+
+ofd @ fclose
Modified: cpu/ppc/olpc/pcinode.fth
===================================================================
--- cpu/ppc/olpc/pcinode.fth 2007-07-23 19:34:43 UTC (rev 487)
+++ cpu/ppc/olpc/pcinode.fth 2007-07-23 19:40:40 UTC (rev 488)
@@ -32,7 +32,6 @@
\ Could do interrupt routing here
;
-[ifdef] notyet
headerless
\ Determine the parent interrupt information (the "interrupt line" in PCI
@@ -43,6 +42,8 @@
\ This table describes the wiring of PCI interrupt pins at the PCI slots
\ to PIRQ inputs on the 82378zb chip. The wiring varies from slot to slot.
+[ifdef] notyet
+
create slot-map
\ Pin A Pin B Pin C Pin D Dev#
@@ -61,9 +62,11 @@
c - 4 * + slot-map + c@ ( pirq#|ff )
dup h# ff = if drop true else false then
;
+[then]
headers
+[ifdef] notyet
: assign-int-line ( phys.hi.func int-pin -- false | int-line true )
dup 0= if 2drop false exit then ( phys.hi.func int-pin# )
1- swap d# 11 rshift h# 1f and ( int-pin0 dev# )
@@ -75,11 +78,16 @@
true
;
+[else]
+.( XXX implement assign-int-line) cr
+: assign-int-line ( phys.hi.func int-pin -- false | int-line true )
+ 2drop false exit
+;
+[then]
-h# 700 encode-int \ Mask of implemented slots
+h# 180 encode-int \ Mask of implemented slots
" PCI 1" encode-string encode+
-" PCI 2" encode-string encode+
-" PCI 3" encode-string encode+ " slot-names" property
+" PCI 2" encode-string encode+ " slot-names" property
[then]
device-end
Added: cpu/ppc/olpc/resetvec.bth
===================================================================
--- cpu/ppc/olpc/resetvec.bth (rev 0)
+++ cpu/ppc/olpc/resetvec.bth 2007-07-23 19:40:40 UTC (rev 488)
@@ -0,0 +1,7 @@
+purpose: Build script for the reset vector startup code
+copyright: Copyright 1997 FirmWorks All Rights Reserved
+
+command: &builder &this
+build-now
+
+fload ${BP}/cpu/ppc/resetvec.fth
Added: cpu/ppc/olpc/start.bth
===================================================================
--- cpu/ppc/olpc/start.bth (rev 0)
+++ cpu/ppc/olpc/start.bth 2007-07-23 19:40:40 UTC (rev 488)
@@ -0,0 +1,76 @@
+purpose: Load file for start.di dropin
+copyright: Copyright 1997 FirmWorks. All rights resrved.
+
+command: &builder &this
+build-now
+
+h# 0ff0.0000 constant /ram
+h# 20.0000 constant /fw-ram
+
+true value stand-init-debug?
+\ false value stand-init-debug?
+
+\needs start-assembling fload ${BP}/cpu/ppc/asmtools.fth
+
+hex
+
+start-assembling
+
+label my-entry
+ 0 , \ To be patched later
+end-code
+
+fload ${BP}/cpu/ppc/olpc/reports.fth
+\ fload ${BP}/cpu/ppc/olpc/initcom1.fth
+
+\ fload ${BP}/cpu/ppc/olpc/mem.fth
+\ fload ${BP}/cpu/ppc/scrub.fth
+
+label start-memory ( -- )
+ mfspr r31,lr
+
+\ init-com1 bl *
+
+\ eagle-mem bl * \ Configure memory
+\ eagle-mem-size bl * \ r7 = actual RAMtop
+ /ram set r7,*
+ mr r30,r7
+
+[ifdef] notdef
+ /fw-ram set r4,* \ Firmware memory size
+ subf r3,r4,r30 \ Firmware memory base address
+ scrub-memory bl *
+
+ set r4,h#4000 \ size of low memory int vectors
+ set r3,0
+ scrub-memory bl *
+[then]
+
+ stw r30,0(r0) \ Actual memory size in low-memory structure
+
+ addi r3,r0,0 \ We don't know the memory speed
+ stw r3,4(r0) \ Memory speed in low-memory structure
+
+ set r3,d#800000000
+ stw r3,8(r0) \ CPU speed in low-memory structure
+
+ set r3,d#200000000
+ stw r3,12(r0) \ Bus speed in low-memory structure
+
+ addi r3,r0,0 \ Null board type
+ stw r3,16(r0) \ Board type in low-memory structure
+
+ /fw-ram set r4,* \ FW memory size, passed to reset code in r4
+ subf r3,r4,r30 \ FW memory base addr., passed to reset code in r3
+
+ mtspr lr,r31
+ bclr 20,0
+end-code
+
+start-memory my-entry put-branch
+
+end-assembling
+
+writing start.di
+asm-base here over - 0 " start" write-dropin
+ofd @ fclose
Modified: cpu/ppc/ppcboot.fth
===================================================================
--- cpu/ppc/ppcboot.fth 2007-07-23 19:34:43 UTC (rev 487)
+++ cpu/ppc/ppcboot.fth 2007-07-23 19:40:40 UTC (rev 488)
@@ -187,7 +187,7 @@
end-code
[then]
-create uboot-entry
+\ create uboot-entry
label rom-cold-code ( r3:fw-RAM-base r4:fw-RAM-size -- )
[ifdef] uboot-entry
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