[OpenBIOS] question for the experts on PII vs. Celeron startup

Ronald G Minnich rminnich at lanl.gov
Wed May 24 12:23:03 CEST 2000

I have been having trouble getting PII to work with memory from powerup. I
just now realized that I'm seeing basically the same problem on the Intel
and SiS motherboards. Engineers at SiS, using the same linuxbios romimage
as I am using, has no troubles on the motherboard BUT: they are using
Celeron. (see the linuxbios web page: I can still get the intel
motherboard up with linuxbios, but I have to let the flash recovery code
run first by twiddling the jumper).

The symptom is that during memory init, at some point the processor seems
to take a trap during a memory write. It is as though some piece of
hardware between the processor and memory is unhappy :-)

I'm working with SiS to try a different motherboard. But: I'm now
wondering if I'm encountering some kind of PII L2 Cache init problem on
the Slot 1 cards I'm using here. I'm very suspicious that I'm seeing a
particular kind of problem on my Slot 1 PII systems that SiS is not seeing
using a Celeron, and that I'm seeing the same kind of problem on both
Intel and SiS mainboards.

Any comments on this? Any thoughts? Anyone know if anything special
happens for L2 cache on a Slot 1 card at powerup? It would probably look
like an IN or OUT to an undocumented address (undocumented since this is
Intel we're talking about here).

p.s. linuxbios: http://www.acl.lanl.gov/linuxbios

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