[OpenBIOS] POST speeds.

[David Christensen]

Don't forget to set the MTRRs (Memory Type and Range Registers I believe) in
the CPU.  Enabling the L2 cache isn't enough, you have to tell the CPU what
memory ranges it can cache.  At a minimum you want to enable write-back on
the 0-640K and 1M-TOM (top-of-memory) memory ranges.  Setting the ROM ranges
to read-only would be good too.

Dave

-----Original Message-----
From: owner-openbios at elvis.informatik.uni-freiburg.de
[mailto:owner-openbios at elvis.informatik.uni-freiburg.de]On Behalf Of
Alan Grimes
Sent: Tuesday, March 21, 2000 11:28 PM
To: openbios at elvis.informatik.uni-freiburg.de
Subject: Re: [OpenBIOS] POST speeds.


> I'm sure you are right. I was clearing the cache disable bit but I
>suppose there is more to do.

I think that's missguided.
My memory tells me that the bit is called "Cache Enable" with

1 = enable
0 = dissable.

That's for the L1 cache, the L2 cache is neccessarily somewhere else in the
MSRs for all Pentium pro and derivatives.

--
The militia whose regulation was referred to by the second ammendment is
the one run by the pentagon.

http://users.erols.com/alangrimes/
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