[OpenBIOS] POST speeds.

Alan Grimes alangrimes at starpower.net
Tue Mar 21 23:27:57 CET 2000

> I'm sure you are right. I was clearing the cache disable bit but I >suppose there is more to do.

I think that's missguided. 
My memory tells me that the bit is called "Cache Enable" with 

1 = enable
0 = dissable. 

That's for the L1 cache, the L2 cache is neccessarily somewhere else in the
MSRs for all Pentium pro and derivatives.

The militia whose regulation was referred to by the second ammendment is
the one run by the pentagon.

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