[OpenBIOS] current ugly pci config code.
Ronald G Minnich
rminnich at lanl.gov
Tue Apr 25 10:48:57 CEST 2000
This is a bash together of niklas ekstrom's code and some linux kernel
code. The intent is to configure the pci bus "enough" so that linux 2.3.99
is happy.
Problems: linux isn't happy. Very early in the game it finds an address
range of 0x0 to 0xffffffff on device0:0c.0, which is totally invalid. It
also thinks IDE is disabled, even though the debug prints show that I'm
turning on the relevant bits. I'm not sure what I'm doing wrong.
All help and comments appreciated.
ron
---------- Forwarded message ----------
Date: Tue, 25 Apr 2000 09:23:32 -0600 (MDT)
From: Ronald G Minnich <rminnich at lanl.gov>
To: "[ISO-8859-1] Niklas Ekström" <t97nek at student.tdb.uu.se>
Subject: Re: [OpenBIOS] PCI config code.
here you are. I yanked some code from linux which does a pretty good job
of figuring out config type.
Formatting sucks right now, I was on a slow dial-up via vi when I did
this.
It sort of seems to work, but not totally. Linux is getting confused by
the BAR settings, to the point that it reads -1 for some things (!).
Also: it seems the BIOSes build address from high memory down, starting at
the highest possible address and working backwards. This kind of makes
some sense, I guess, but who knows. One possibility would be to start the
address at a high number (e.g. 0xfd000000) and decrement it.
Also, I'm pretty sure we should not try to configure AGP or even any type
of VGA hardware. The code doesn't do that just yet.
Ignore my NextMemAddr and NextIoAddr functions, they are not used.
Anything you can do would be great.
Thanks
ron
-------------- next part --------------
/*
* Low-Level PCI Support for PC
*
* (c) 1999--2000 Martin Mares <mj at suse.cz>
*/
#include <sys/types.h>
#include <asm/io.h>
#include <pci.h>
void display(char []);
void printint(unsigned int);
static const struct pci_ops *conf;
struct pci_ops {
int (*read_byte)(u8 bus, int devfn, int where, u8 *val);
int (*read_word)(u8 bus, int devfn, int where, u16 *val);
int (*read_dword)(u8 bus, int devfn, int where, u32 *val);
int (*write_byte)(u8 bus, int devfn, int where, u8 val);
int (*write_word)(u8 bus, int devfn, int where, u16 val);
int (*write_dword)(u8 bus, int devfn, int where, u32 val);
};
/*
* Direct access to PCI hardware...
*/
/*
* Functions for accessing PCI configuration space with type 1 accesses
*/
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
static int pci_conf1_read_config_byte(unsigned char bus, int devfn, int where, u8 *value)
{
outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
*value = inb(0xCFC + (where&3));
return 0;
}
static int pci_conf1_read_config_word(unsigned char bus, int devfn, int where, u16 *value)
{
outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
*value = inw(0xCFC + (where&2));
return 0;
}
static int pci_conf1_read_config_dword(unsigned char bus, int devfn, int where, u32 *value)
{
outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
*value = inl(0xCFC);
return 0;
}
static int pci_conf1_write_config_byte(unsigned char bus, int devfn, int where, u8 value)
{
outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
outb(value, 0xCFC + (where&3));
return 0;
}
static int pci_conf1_write_config_word(unsigned char bus, int devfn, int where, u16 value)
{
outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
outw(value, 0xCFC + (where&2));
return 0;
}
static int pci_conf1_write_config_dword(unsigned char bus, int devfn, int where, u32 value)
{
outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
outl(value, 0xCFC);
return 0;
}
#undef CONFIG_CMD
const struct pci_ops pci_direct_conf1 = {
pci_conf1_read_config_byte,
pci_conf1_read_config_word,
pci_conf1_read_config_dword,
pci_conf1_write_config_byte,
pci_conf1_write_config_word,
pci_conf1_write_config_dword
};
/*
* Functions for accessing PCI configuration space with type 2 accesses
*/
#define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where)
#define FUNC(devfn) (((devfn & 7) << 1) | 0xf0)
#define SET(bus,devfn) if (devfn & 0x80) return -1;outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA);
static int pci_conf2_read_config_byte(unsigned char bus, int devfn, int where, u8 *value)
{
SET(bus, devfn);
*value = inb(IOADDR(devfn,where));
outb (0, 0xCF8);
return 0;
}
static int pci_conf2_read_config_word(unsigned char bus, int devfn, int where, u16 *value)
{
SET(bus, devfn);
*value = inw(IOADDR(devfn,where));
outb (0, 0xCF8);
return 0;
}
static int pci_conf2_read_config_dword(unsigned char bus, int devfn, int where, u32 *value)
{
SET(bus, devfn);
*value = inl (IOADDR(devfn,where));
outb (0, 0xCF8);
return 0;
}
static int pci_conf2_write_config_byte(unsigned char bus, int devfn, int where, u8 value)
{
SET(bus, devfn);
outb (value, IOADDR(devfn,where));
outb (0, 0xCF8);
return 0;
}
static int pci_conf2_write_config_word(unsigned char bus, int devfn, int where, u16 value)
{
SET(bus, devfn);
outw (value, IOADDR(devfn,where));
outb (0, 0xCF8);
return 0;
}
static int pci_conf2_write_config_dword(unsigned char bus, int devfn, int where, u32 value)
{
SET(bus, devfn);
outl (value, IOADDR(devfn,where));
outb (0, 0xCF8);
return 0;
}
#undef SET
#undef IOADDR
#undef FUNC
const struct pci_ops pci_direct_conf2 = {
pci_conf2_read_config_byte,
pci_conf2_read_config_word,
pci_conf2_read_config_dword,
pci_conf2_write_config_byte,
pci_conf2_write_config_word,
pci_conf2_write_config_dword
};
/*
* Before we decide to use direct hardware access mechanisms, we try to do some
* trivial checks to ensure it at least _seems_ to be working -- we just test
* whether bus 00 contains a host bridge (this is similar to checking
* techniques used in XFree86, but ours should be more reliable since we
* attempt to make use of direct access hints provided by the PCI BIOS).
*
* This should be close to trivial, but it isn't, because there are buggy
* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
*/
static int pci_sanity_check(const struct pci_ops *o)
{
u16 x;
u8 bus;
int devfn;
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_VENDOR_ID_COMPAQ 0x0e11
#define PCI_VENDOR_ID_INTEL 0x8086
for(devfn=0; devfn < 0x100; devfn++)
if ((!o->read_word(bus,devfn, PCI_CLASS_SUB_CODE, &x) &&
(x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
(!o->read_word(bus, devfn, PCI_VENDOR_ID, &x) &&
(x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
return 1;
display("PCI: Sanity check failed\n");
return 0;
}
static const struct pci_ops * pci_check_direct(void)
{
unsigned int tmp;
unsigned long flags;
/*
* Check if configuration type 1 works.
*/
{
outb (0x01, 0xCFB);
tmp = inl (0xCF8);
outl (0x80000000, 0xCF8);
if (inl (0xCF8) == 0x80000000 &&
pci_sanity_check(&pci_direct_conf1)) {
outl (tmp, 0xCF8);
display("PCI: Using configuration type 1\n");
return &pci_direct_conf1;
}
outl (tmp, 0xCF8);
}
/*
* Check if configuration type 2 works.
*/
{
outb (0x00, 0xCFB);
outb (0x00, 0xCF8);
outb (0x00, 0xCFA);
if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
pci_sanity_check(&pci_direct_conf2)) {
display("PCI: Using configuration type 2\n");
return &pci_direct_conf2;
}
}
return 0;
}
/*
* GNUBIOS
* Copyright 1999, 2000 Niklas Ekström
*
* PCI Implementation
*/
static u32 NextMemAddr = 0x80000000; /* 2GB border */
static u32 NextIoAddr = 0x1000; /* Above all legacy IO */
static u8 MaxBus = 0; /* The highest PCI bus number */
u32 NewPciMem(u32 size)
{
/* well, bridges appear to like 64K alignment. Make it easy, just do that.
* it's also good for VM-aware OSes: you get a free red-zone for all the
* little registers
*/
#define ROUNDPCI (64*1024-1)
u32 NewAddr;
NewAddr = NextMemAddr;
NextMemAddr = (NextMemAddr + size + ROUNDPCI) & (~ROUNDPCI);
display("NewPciMem: alloc");
printint(NextMemAddr);
display("\n");
return NewAddr;
}
u32 NewPciIo(u32 size)
{
u32 NewIoAddr = NextIoAddr;
NextIoAddr += size;
display("NewPciMem: alloc");
printint(NextIoAddr);
display("\n");
return NewIoAddr;
}
u32
PciReadDword(u8 bus, int devfn, int reg)
{
u32 val;
conf->read_dword(bus, devfn, reg, &val);
return val;
}
u16
PciReadWord(u8 bus, int devfn, int reg)
{
u16 val;
conf->read_word(bus, devfn, reg, &val);
return val;
}
u8
PciReadByte(u8 bus, int devfn, int reg)
{
u8 val;
conf->read_byte(bus, devfn, reg, &val);
return val;
}
void
PciWriteDword(u8 bus, int devfn, int reg, u32 val)
{
conf->write_dword(bus, devfn, reg, val);
}
void
PciWriteWord(u8 bus, int devfn, int reg, u16 val)
{
conf->write_word(bus, devfn, reg, val);
}
void
PciWriteByte(u8 bus, int devfn, int reg, u8 val)
{
conf->write_byte(bus, devfn, reg, val);
}
/* what we have to do:
* increment bus #, and set it into the device.
* track the current base io and memory addresses
* iterate over the bus
* get sizing stuff stuff and stuff it into the bride
* stuff last bus # into the subordinate #
* return ...
*/
void
PciAllocateResourcesBridge(bus, devfn)
{
int PciAllocateResourcesBus( u8 bus );
u32 BaseMemAddr;
u32 BaseIoAddr = NextIoAddr;
u16 command;
display("bridge devfn is "); printint(devfn); display("\n");
/* take it off line */
command = PciReadWord( bus, devfn, PCI_COMMAND);
command &= ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY);
PciWriteWord( bus, devfn, PCI_COMMAND, command );
/* round nextmemaddr up to a 64k boundary ... it's a 16-bit register */
NextMemAddr = ((NextMemAddr>>16)+1)<<16;
BaseMemAddr = NextMemAddr;
MaxBus = bus + 1;
/* now set this into the starting bus # register. */
/* hard to believe we need this ... */
PciWriteByte(bus, devfn, PCI_PRIMARY_BUS, bus);
PciWriteByte(bus, devfn, PCI_SECONDARY_BUS, MaxBus);
/* now scan. This could recurse ... */
display("recurse to bus "); printint(MaxBus); display("\n");
PciAllocateResourcesBus(MaxBus);
display("back from bus "); printint(bus+1); display("\n");
display("subordinate is "); printint(MaxBus); display("\n");
display("conf is "); printint(conf); display("\n");
/* end of scan, set maxbus into the subordinate */
PciWriteByte(bus, devfn, PCI_SUBORDINATE_BUS, MaxBus);
/* set iosize and address */
/* we need a PCI manual. Should we (I assume) set a bit in the
* cmd register if I/O will work? I'm unsure about bridges. -- RGM
*/
if (NextIoAddr > BaseIoAddr) {
command |= PCI_COMMAND_IO;
PciWriteWord(bus, devfn, PCI_IO_BASE, BaseIoAddr);
PciWriteWord(bus, devfn, PCI_IO_LIMIT, NextIoAddr-1);
}
else {
PciWriteWord(bus, devfn, PCI_IO_BASE, 0);
PciWriteWord(bus, devfn, PCI_IO_LIMIT, 0);
}
display("I wrote the io as "); printint(BaseIoAddr);
printint(NextIoAddr); display("\n");
if (NextMemAddr > BaseMemAddr) {
PciWriteWord(bus, devfn, PCI_MEMORY_BASE, BaseMemAddr>>16);
NextMemAddr = ((NextMemAddr>>16)+1)<<16;
PciWriteWord(bus, devfn, PCI_MEMORY_LIMIT, NextMemAddr>>16);
command |= PCI_COMMAND_MEMORY;
} else {
PciWriteWord(bus, devfn, PCI_MEMORY_BASE, 0);
PciWriteWord(bus, devfn, PCI_MEMORY_LIMIT, 0);
}
display("I wrote the mem as "); printint(BaseMemAddr);
printint(NextMemAddr); display("\n");
PciWriteWord( bus, devfn, PCI_COMMAND, command );
display("bridge exits command is "); printint(command); display("\n");
}
int PciAllocateResourcesBus( u8 bus )
{
int devfn;
u16 command;
u8 reg;
u32 addr;
u8 membits;
display("PciAllocateResourcesBus for bus "); printint(bus);
display("\n");
for( devfn = 0; devfn < 256; devfn++ )
{
u8 type;
if( PciReadDword( bus, devfn, PCI_VENDOR_ID ) == 0xffffffff )
{
devfn |= 0x07;
continue;
}
type = PciReadByte( bus, devfn, PCI_HEADER_TYPE );
type &= 0x7f;
display("check devfn "); printint(devfn); display("\n");
if (type == PCI_HEADER_TYPE_P2P)
PciAllocateResourcesBridge(bus, devfn);
/* other than that, it better be 0 ... */
if( type )
continue;
command = 0;
for( reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4 )
{
PciWriteDword( bus, devfn, reg, 0xffffffff );
addr = PciReadDword( bus, devfn, reg );
if( addr == 0 )
continue;
if( (addr & PCI_ADDR_SPACE) == PCI_ADDR_SPACE_MEM ) /* MEM */
{
command |= PCI_COMMAND_MEMORY;
membits = addr & 0xf;
addr &= 0xfffffff0;
NextMemAddr = (NextMemAddr + ~addr) & addr;
PciWriteDword( bus, devfn, reg, NextMemAddr | membits );
display("mallocate "); printint(NextMemAddr);
display("\n");
NextMemAddr += ~addr + 1;
}
else /* IO */
{
command |= PCI_COMMAND_IO;
addr &= 0xfffffffc;
addr |= 0xffff0000; // The IO address space is only 16 bits
NextIoAddr = (NextIoAddr + ~addr) & addr;
display("iallocate "); printint(NextIoAddr);
display("\n");
PciWriteDword( bus, devfn, reg, NextIoAddr | PCI_ADDR_SPACE_IO );
NextIoAddr += ~addr + 1;
}
}
PciWriteWord( bus, devfn, PCI_COMMAND, command );
display("write command "); printint(command); display("\n");
PciWriteDword( bus, devfn, PCI_ROM_BASE_ADDRESS, 0xffffffff );
addr = PciReadDword( bus, devfn, PCI_ROM_BASE_ADDRESS );
if( addr != 0 )
{
addr &= 0xfffff800;
NextMemAddr = (NextMemAddr + ~addr) & addr;
PciWriteDword( bus, devfn, PCI_ROM_BASE_ADDRESS, NextMemAddr | PCI_ROM_BASE_ENABLED );
NextMemAddr += ~addr + 1;
}
}
}
int PciAllocateResources()
{
conf = &pci_direct_conf1;
conf = pci_check_direct();
return( PciAllocateResourcesBus( 0 ) );
}
#if 0
int PciFindDevice( u8 bus, u32 venddev, int devfn )
{
u32 tmp;
for ( ; devfn < 256; devfn++ )
{
tmp = PciReadDword( bus, devfn, PCI_VENDOR_ID );
if( tmp == 0xffffffff )
devfn |= 0x07;
else if( tmp == venddev )
return( devfn );
}
return( -1 );
}
int PciFindClass( u8 bus, u32 devclass, int devfn )
{
devclass <<= 8;
for ( ; devfn < 256; devfn++ )
{
if( PciReadDword( bus, devfn, PCI_VENDOR_ID ) == 0xffffffff )
devfn |= 0x07;
else if( (PciReadDword( bus, devfn, PCI_CLASS_REVISION ) & PCI_CLASS_MASK) == devclass )
return( devfn );
}
return( -1 );
}
#endif
-------------- next part --------------
/*
* GNUBIOS
* Copyright 1999, 2000 Niklas Ekström
*
* PCI Interface
*/
#ifndef GNUBIOS_PCI_H
#define GNUBIOS_PCI_H
/* some basic types we use nowhere else */
typedef unsigned char u8;
typedef unsigned short u16;
typedef unsigned long u32;
/* PCI Configuration Space Entries */
#define PCI_VENDOR_ID 0x00
#define PCI_DEVICE_ID 0x02
#define PCI_COMMAND 0x04
#define PCI_COMMAND_IO 0x0001
#define PCI_COMMAND_MEMORY 0x0002
#define PCI_COMMAND_MASTER 0x0004
#define PCI_COMMAND_SPECIAL 0x0008
#define PCI_COOMAND_MEMWAI 0x0010
#define PCI_COMMAND_VGA_SNOOP 0x0020
#define PCI_COMMAND_PARITY 0x0040
#define PCI_COMMAND_WAIT 0x0080
#define PCI_COMMAND_SERR 0x0100
#define PCI_COMMAND_FAST_B2B 0x0200
#define PCI_STATUS 0x06
#define PCI_STATUS_66_CAPABLE 0x0020
#define PCI_STATUS_UDF 0x0040
#define PCI_STATUS_FAST_B2B 0x0080
#define PCI_STATUS_PARITY 0x0100
#define PCI_STATUS_DEVSEL_MASK 0x0600
#define PCI_STATUS_DEVSEL_FAST 0x0000
#define PCI_STATUS_DEVSEL_MEDIUM 0x0200
#define PCI_STATUS_DEVSEL_SLOW 0x0400
#define PCI_STATUS_SIG_TARGET_ABORT 0x0800
#define PCI_STATUS_RCV_TARGET_ABORT 0x1000
#define PCI_STATUS_RCV_MASTER_ABORT 0x2000
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000
#define PCI_STATUS_PARITY_ERROR 0x8000
#define PCI_CLASS_REVISION 0x08
#define PCI_CLASS_MASK 0xffffff00
#define PCI_REVISION_ID 0x08
#define PCI_CLASS_PROG_IF 0x09
#define PCI_CLASS_SUB_CODE 0x0a
#define PCI_CLASS_BASE_CODE 0x0b
#define PCI_CACHE_LINE_SIZE 0x0c
#define PCI_LATENCY_TIMER 0x0d
#define PCI_HEADER_TYPE 0x0e
#define PCI_HEADER_MULTIFUNC 0x80
#define PCI_HEADER_TYPE_0 0x00
#define PCI_HEADER_TYPE_P2P 0x01
#define PCI_BIST 0x0f
#define PCI_BIST_COMPCODE_MASK 0x0f
#define PCI_BIST_START 0x40
#define PCI_BIST_CAPABLE 0x80
/* Type 00h Configuration Space Header */
#define PCI_BASE_ADDRESS_0 0x10
#define PCI_BASE_ADDRESS_1 0x14
#define PCI_BASE_ADDRESS_2 0x18
#define PCI_BASE_ADDRESS_3 0x1c
#define PCI_BASE_ADDRESS_4 0x20
#define PCI_BASE_ADDRESS_5 0x24
#define PCI_ADDR_SPACE 0x01
#define PCI_ADDR_SPACE_MEM 0x00
#define PCI_ADDR_SPACE_IO 0x01
#define PCI_ADDR_MEM_TYPE_MASK 0x06
#define PCI_ADDR_MEM_TYPE_32 0x00
#define PCI_ADDR_MEM_TYPE_1M 0x02
#define PCI_ADDR_MEM_TYPE_64 0x04
#define PCI_ADDR_MEM_PREFETCH 0x08
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
#define PCI_SUBSYSTEM_ID 0x2e
#define PCI_ROM_BASE_ADDRESS 0x30
#define PCI_ROM_BASE_ENABLED 0x01
#define PCI_INTERRUPT_LINE 0x3c
#define PCI_INTERRUPT_PIN 0x3d
#define PCI_MIN_GNT 0x3e
#define PCI_MAX_LAT 0x3f
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
#define PCI_IO_LIMIT 0x1d
#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
#define PCI_IO_RANGE_TYPE_16 0x00
#define PCI_IO_RANGE_TYPE_32 0x01
#define PCI_IO_RANGE_MASK ~0x0f
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
#define PCI_MEMORY_LIMIT 0x22
#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
#define PCI_MEMORY_RANGE_MASK ~0x0f
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
#define PCI_PREF_MEMORY_LIMIT 0x26
#define PCI_PREF_RANGE_TYPE_MASK 0x0f
#define PCI_PREF_RANGE_TYPE_32 0x00
#define PCI_PREF_RANGE_TYPE_64 0x01
#define PCI_PREF_RANGE_MASK ~0x0f
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
#define PCI_PREF_LIMIT_UPPER32 0x2c
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
#define PCI_IO_LIMIT_UPPER16 0x32
/* 0x34-0x3b is reserved */
#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL 0x3e
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
int PciFindDevice( u8 bus, u32 venddev, int devfn );
int PciFindClass( u8 bus, u32 devclass, int devfn);
int PciAllocateResources();
#endif /* GNUBIOS_PCI_H */
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