[OpenBIOS] Intel holding back information

Niklas Ekström t97nek at student.tdb.uu.se
Sun Aug 8 13:59:29 CEST 1999

On Sat, 7 Aug 1999, David J. Coffin wrote:
>      You cannot get a DRAM-sizing algorithm from Intel with-
> out signing an NDA, and the NDA forbids you to share your
> source code without Intel's written permission.

Ok, like I suspected :/... (I was pretty certain that someone on this list
could confirm this! :-)

>      VIA Technologies publishes their DRAM-sizing algorithms
> without restriction.  The VIA 580VP chipset matches the Intel
> 430FX almost bit-for-bit, so this is a good place to start.

Great tip, thanks!

I do think that I have an idea on how to detect the DRAM sizes. So if I
write the algorithm here, you or someone else can comment on it and say if
you think it will work. Here goes:

disable all caching (if it isn't already disabled (which it probably is));

set all DRAM Boundary registers (DRBs) to it's maximum value (63 * 4MB), \
  which is >128MB which is the most the chipset can use;

previous_drb_val = 0;    // variable used below

for (n = 0; n < 5; n++) {

  write (some randon) dword of data, k != 0, to address \ 
   previous_drb_val * 4MB and read back y from the same address;

  if (y != k) {
    previous_drb_val += 0;    // NOP
    write previous_drb_val to DRB reg n;
    continue;    // for next n

  for (j = 1; j <= 16; j++) {   // 16 * 4MB is the most a row can hold

    write (some random) dword of data, p != 0, to address \
      (previous_drb_val + j) * 4MB;      // check for wrap-around
    read back y from address previous_drb_val * 4MB;

    if (y == p) {
      previous_drb_val += j;
      write previous_drb_val to DRB reg n;

And that should be it (ofcourse the algorithm must be written without the
use of the stack or any other memory).

On the 440BX, DRAM-sizing seems much less complicated, using the Serial
Presence Detect (SPD) of the 168-pin DIMMs (correct?).

>      For an example of actual code, disassemble an Award,
> AMI, or Phoenix BIOS.  Don't read the BIOS from shadow RAM;
> copy it off the chip or find it on the web.  The DRAM- and
> cache-sizing code are easy to find, because most everything
> else is compressed to resemble random noise.

I have been thinking about doing that, but wouldn't that make me unable to
write the bios after that (legally that is) ?

/ Niklas

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