[flashrom] When flashrom support Intel Purley platform Lewisburg PCH?

Wed Sep 6 03:39:14 CEST 2017

Hi David,

I can't paste the log in https://paste.flashrom.org/. it prompts 'Wrong
captcha'. The attachment is log file, The fail is same as before.
I'm not sure if it's related to ichspi.c num_freg = 12.
In our image, we used the last region(No. 15), when reading this region,
failed.

2017-09-02 4:47 GMT+08:00 David Hendricks <dhendricks at fb.com>:

> Hi Sandy,
>
> I updated the flashrom code to better take into account differences with
> Lewisburg, including the number of FREG registers as you point out:
> https://review.coreboot.org/#/c/20922/
>
>
> When you have a chance, please and try again (using -V). You can
> copy+paste your result here for convenience: https://paste.flashrom.org/.
> Flashrom -- File upload serivce <https://paste.flashrom.org/>
> paste.flashrom.org
> Welcome to flashrom's file upload service Please post only
> flashrom/coreboot/seabios or other firmware related contents. Post a new
> paste You can either post text ...
>
> ------------------------------
> *From:* flashrom <flashrom-bounces at flashrom.org> on behalf of Sandy Zhang
> <sanzhang at celestica.com>
> *Sent:* Monday, August 14, 2017 4:36:00 AM
> *To:* David Hendricks
> *Cc:* flashrom at flashrom.org
> *Subject:* Re: [flashrom] When flashrom support Intel Purley platform
> Lewisburg PCH?
>
> Hi David,
>
> Lewisburg PCH defines sixty SPI regions, but from the code in ichspi.c, I
> find it defines only 10 regions, is this the reason about only 10 regions
> was described in the log file?
>
> code as below: (num_freg define the spi regions)
>
> int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
> {
> ...
>         ...
>         ...
> /* Moving registers / bits */
> if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) {
> num_freg = 10;
> num_pr = 6;
> reg_pr0 = PCH100_REG_FPR0;
> swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
> swseq_data.reg_preop = PCH100_REG_PREOP;
> swseq_data.reg_optype = PCH100_REG_OPTYPE;
> swseq_data.reg_opmenu = PCH100_REG_OPMENU;
> hwseq_data.addr_mask = PCH100_FADDR_FLA;
> hwseq_data.only_4k = true;
> hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
> }
>
> 2017-08-14 14:23 GMT+08:00 David Hendricks <david.hendricks at gmail.com>:
>
>> On Sun, Aug 13, 2017 at 6:26 PM, Sandy Zhang <sanzhang at celestica.com>
>> wrote:
>>
>>> Hi David,
>>>
>>> I'm inline.
>>>
>>
>> I don't see your responses. Did you intend to reply to my comments?
>>
>>
>>>
>>> 2017-08-14 9:17 GMT+08:00 David Hendricks <david.hendricks at gmail.com>:
>>>
>>>> Hi Sandy,
>>>>
>>>> Responses in-line.
>>>>
>>>> On Fri, Aug 11, 2017 at 1:38 AM, Sandy Zhang <sanzhang at celestica.com>
>>>> wrote:
>>>>
>>>>> Hi David,
>>>>>
>>>>>      Sorry, I have a doubt about the range outside, from the binary
>>>>> map, we can find the Spare 3 Region size is 0x00FFFFFF - 0xFF0000 + 1 =
>>>>> 0x10000, and the binary size map to this range is also 0x10000, they are
>>>>> equal, why outside was happened? and can you tell me how to update the
>>>>> binary region's range defined in the flash description?
>>>>>
>>>>> Start (hex)    End (hex)    Length (hex)    Area Name
>>>>> -----------    ---------    ------------    ---------
>>>>> ...
>>>>> ...
>>>>> ....
>>>>> 00FF0000       00FFFFFF     00010000        Spare 3 Region
>>>>> 01000000       01FFFFFF     01000000        BIOS Region
>>>>>
>>>>
>>>> The Flash Region registers (BIOS_FREGn) define the boundaries of each
>>>> region. I don't see where 0xa36000-0xffffff is covered:
>>>> 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff)
>>>> is read-write.
>>>> 0x58: 0x1fff1000 FREG1: BIOS region (0x01000000-0x01ffffff) is
>>>> read-write.
>>>> 0x5C: 0x0a250003 FREG2: Management Engine region
>>>> (0x00003000-0x00a25fff) is read-write.
>>>> 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff)
>>>> is read-write.
>>>> 0x64: 0x00007fff FREG4: Platform Data region is unused.
>>>> 0x68: 0x0a350a26 FREG5: unknown region (0x00a26000-0x00a35fff) is
>>>> read-write.
>>>> 0x6C: 0x00007fff FREG6: unknown region is unused.
>>>> 0x70: 0x00007fff FREG7: unknown region is unused.
>>>> 0x74: 0x00007fff FREG8: unknown region is unused.
>>>> 0x78: 0x00007fff FREG9: unknown region is unused.
>>>>
>>>> You might also need to set permissions for the "BIOS" master (i.e.
>>>> flashrom running on the CPU) via BRWA and BRRA in the FRACC register.
>>>>
>>>>  In addition, from flash log file(please see attachment
>>>>> "Lewisburg_W25Q256.log"), it shows:
>>>>> Found Programmer flash chip "Opaque flash chip" (32768 kB,
>>>>> Programmer-specific) mapped at physical address 0x0000000000000000.
>>>>>  but, my flash chip is "Winbond flash chip", what do you think about
>>>>> this?
>>>>>
>>>>
>>>> This is OK. Intel hardware sequencing is an "opaque" programmer
>>>> interface since flashrom does not directly send NOR flash commands via a
>>>> raw SPI interface. For hardware sequencing we use the FCYCLE field as our
>>>> command interface to the SPI flash.
>>>>
>>>>
>>>
>>>
>>> --
>>>
>>> *Best Regard!*
>>>
>>> *Sandy Zhang (* 张立康*)*
>>> *BIOS Engineer*
>>> *Global Design Service*
>>> *Celestica(Shanghai) R&D Center, China*
>>> *Mail: sanzhang at celestica.com <viterzho at celestica.com>*
>>> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
>>> *Phone: (+86)021-61006028-7623*
>>>
>>
>>
>
>
> --
>
> *Best Regard!*
>
> *Sandy Zhang (* 张立康*)*
> *BIOS Engineer*
> *Global Design Service*
> *Celestica(Shanghai) R&D Center, China*
> *Mail: sanzhang at celestica.com <viterzho at celestica.com>*
> *Mobile: (+86)15965353952 <+86%20159%206535%203952>*
> *Phone: (+86)021-61006028-7623*
>

-- 

*Best Regard!*

*Sandy Zhang (* 张立康*)*
*BIOS Engineer*
*Global Design Service*
*Celestica(Shanghai) R&D Center, China*
*Mail: sanzhang at celestica.com <viterzho at celestica.com>*
*Mobile: (+86)15965353952*
*Phone: (+86)021-61006028-7623*
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