[flashrom] [coreboot] Erase failure on Sapphire Pure Platinum H61 with coreboot

[Nicola Corna]

September 3, 2017 12:24 AM, "Nico Huber" <nico.h at gmx.de> wrote:

> TLDR; it would be a lot slower.
> 
> Alas, there is no usual byte-program mode. Most chips do a 256B page
> program which uses op code 0x02 too. For the SST25VF032B it's really a
> 1B program. If you use that instead of the AAI write, you get lots of
> overhead (6B total, if I'm not mistaken, instead of ~1.5B per actual
> written byte + twice the polling for write-in-progress).
> 
> Nico

Thank you.

I've noticed that some boards have already an extra "finalize", which overrides
the default opmenu and optype (see mb/siemens/mc_bdx1/mainboard.c): should I
copy that implementation or add the configurations in the device tree and modify
every sb/intel/*/pch.h (as you suggested before)?

Nicola