[flashrom] Erase failure on Sapphire Pure Platinum H61 with coreboot

Nico Huber nico.h at gmx.de
Sat Sep 2 17:32:27 CEST 2017


Hi Nicola,

On 02.09.2017 15:06, Nicola Corna wrote:
> Hi,
> 
> I have a Sapphire Pure Platinum H61 with coreboot and flashrom fails
> to erase the flash chip (corrupting the image); attached you can find
> the log.

oh, the error message is rather subtle. I'll spare you the details.
The actual problem is that your flash chip is rather unlikely and the
write aai (0xad) and write disable (0x04) op codes are not in the list
coreboot set as allowed op codes:

> 0x98: 0x05030201 (OPMENU)
> 0x9C: 0x0bd89f20 (OPMENU+4)

Each byte here is one allowed op code. Now, to makes things worse, core-
boot and flashrom use different sets of codes (e.g. flashrom uses read
(0x03), coreboot uses fast read (0x0b)). The currently hardcoded list
is define in sb/intel/bd82x6x/pch.h for your board. For full compatibi-
lity with every coreboot feature that uses the flash (e.g. elog, flash
console) and flashrom, you'd have to find a set of op codes that always
works.

One question, though, is this the original flash chip of your board? If
not, any effort to make it supported is probably wasted. If it is the
original chip, I'd go this way: Make the op menu that coreboot sets in
bd82x6x/finalize.c configurable through the devicetree. I'd leave the
defaults from pch.h in place in case the devietree settings are left at
zero.

>From the original op menu these are probably unneeded: byte program
(0x02), either one of the block erasers (0x20 and 0xd8) and the fast
read (0x0b).

Probably working (with flashrom) op menu for your chip:

0x05030201
0x04ad9f20

> 
> Before coreboot's commit d533b16 the internal flashing worked after a
> fresh start, while after a S3 resume it failed with the same error.
> Starting from this commit, the internal flashing doesn't work at all.

For the record, this commit enabled the SPI lockdown (e.g. locked the
OPMENU). Which was previously only set after resume by accident.

> 
> As suggested by Nico Huber, I tried with `-p
> internal:ich_spi_mode=hwseq`, without success (log attached).
> 

Ah, I see why it didn't detect a chip. In the hardware sequencing mode,
the actual communication with the flash chip is left to the PCH. We
can't even probe for the chip, so giving it `-c SST25VF032B` makes it
fail.

Nico
-------------- next part --------------
flashrom v0.9.9-r1954 on Linux 4.12.0-1-amd64 (x86_64)
flashrom is free software, get the source code at https://flashrom.org

flashrom was built with libpci 3.5.2, GCC 6.3.0 20170221, little endian
Command line (7 args): flashrom -VVV -p internal -c SST25VF032B -w build/coreboot.rom
Calibrating delay loop... OS timer resolution is 1 usecs, 3887M loops per second, 10 myus = 10 us, 100 myus = 139 us, 1000 myus = 1016 us, 10000 myus = 10009 us, 4 myus = 13 us, OK.
Initializing internal programmer
Found candidate at: 00000500-00000510
Found coreboot table at 0x00000500.
Found candidate at: 00000000-00000908
Found coreboot table at 0x00000000.
coreboot table found at 0x7fedd000.
coreboot header(24) checksum: fa8a table(2312) checksum: 6aa1 entries: 30
Vendor ID: Sapphire, part ID: Pure Platinum H61
Using Internal DMI decoder.
page_size=1000
pre-rounding:  start=0x00000000000f0000, len=0x10000, end=0x0000000000100000
post-rounding: start=0x00000000000f0000, len=0x10000, end=0x0000000000100000
page_size=1000
pre-rounding:  start=0x000000007fea7020, len=0x212, end=0x000000007fea7232
post-rounding: start=0x000000007fea7000, len=0x1000, end=0x000000007fea8000
DMI string chassis-type: "Desktop"
page_size=1000
pre-rounding:  start=0x00007efcba635020, len=0x212, end=0x00007efcba635232
post-rounding: start=0x00007efcba635000, len=0x1000, end=0x00007efcba636000
page_size=1000
pre-rounding:  start=0x00007efcba636000, len=0x10000, end=0x00007efcba646000
post-rounding: start=0x00007efcba636000, len=0x10000, end=0x00007efcba646000
DMI string system-manufacturer: "Sapphire"
DMI string system-product-name: "Pure Platinum H61"
DMI string system-version: "1.0"
DMI string baseboard-manufacturer: "Sapphire"
DMI string baseboard-product-name: "Pure Platinum H61"
DMI string baseboard-version: "1.0"
Found chipset "Intel H61" with PCI ID 8086:1c5c.
Enabling flash write... Root Complex Register Block address = 0xfed1c000
page_size=1000
pre-rounding:  start=0x00000000fed1c000, len=0x4000, end=0x00000000fed20000
post-rounding: start=0x00000000fed1c000, len=0x4000, end=0x00000000fed20000
GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI)
Top Swap: enabled (A16(+) inverted)
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode enabled
0xffe00000/0xffa00000 FWH decode enabled
0xffd80000/0xff980000 FWH decode enabled
0xffd00000/0xff900000 FWH decode enabled
0xffc80000/0xff880000 FWH decode enabled
0xffc00000/0xff800000 FWH decode enabled
0xff700000/0xff300000 FWH decode enabled
0xff600000/0xff200000 FWH decode enabled
0xff500000/0xff100000 FWH decode enabled
0xff400000/0xff000000 FWH decode enabled
Maximum FWH chip size: 0x100000 bytes
SPI Read Configuration: prefetching enabled, caching enabled, 
BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x00007efcba642000 + 0x3800
0x04: 0xc008 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=0, FDV=1, FLOCKDN=1
Warning: SPI Configuration Lockdown activated.
The Flash Descriptor Override Strap-Pin is set. Restrictions implied by
the Master Section of the flash descriptor are NOT in effect. Please note
that Protected Range (PR) restrictions still apply.
Reading OPCODES... done
        OP        Type      Pre-OP
op[0]: 0x01, write w/o addr, none
op[1]: 0x02, write w/  addr, none
op[2]: 0x03, read  w/  addr, none
op[3]: 0x05, read  w/o addr, none
op[4]: 0x20, write w/  addr, none
op[5]: 0x9f, read  w/o addr, none
op[6]: 0xd8, write w/  addr, none
op[7]: 0x0b, read  w/  addr, none
Pre-OP 0: 0x06, Pre-OP 1: 0x50
0x06: 0x0000 (HSFC)
HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0
0x08: 0x00000000 (FADDR)
0x50: 0x0000ffff (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write.
0x58: 0x03ff0018 FREG1: BIOS region (0x00018000-0x003fffff) is read-write.
0x5C: 0x00170001 FREG2: Management Engine region (0x00001000-0x00017fff) is read-write.
0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused.
0x64: 0x00001fff FREG4: Platform Data region is unused.
0x74: 0x00000000 (PR0 is unused)
0x78: 0x00000000 (PR1 is unused)
0x7C: 0x00000000 (PR2 is unused)
0x80: 0x00000000 (PR3 is unused)
0x84: 0x00000000 (PR4 is unused)
0x90: 0x80 (SSFS)
SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0
0x91: 0xf94400 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=4, SME=0, SCF=1
0x94: 0x5006     (PREOP)
0x96: 0xb32d     (OPTYPE)
0x98: 0x05030201 (OPMENU)
RDSR READ BYPR WRSR
0x9C: 0x0bd89f20 (OPMENU+4)
FAST BED8 RDID BE20
0xA0: 0x00000000 (BBAR)
0xC4: 0x00802009 (LVSCC)
LVSCC: BES=0x1, WG=0, WSR=1, WEWS=0, EO=0x20, VCL=1
0xC8: 0x00002009 (UVSCC)
UVSCC: BES=0x1, WG=0, WSR=1, WEWS=0, EO=0x20
0xD0: 0x00000000 (FPB)
Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.
=== Content Section ===
FLVALSIG 0x0ff0a55a
FLMAP0   0x02040003
FLMAP1   0x12100206
FLMAP2   0x00210120

--- Details ---
NR          (Number of Regions):                     3
FRBA        (Flash Region Base Address):         0x040
NC          (Number of Components):                  1
FCBA        (Flash Component Base Address):      0x030
ISL         (ICH/PCH Strap Length):                 18
FISBA/FPSBA (Flash ICH/PCH Strap Base Address):  0x100
NM          (Number of Masters):                     3
FMBA        (Flash Master Base Address):         0x060
MSL/PSL     (MCH/PROC Strap Length):                 1
FMSBA       (Flash MCH/PROC Strap Base Address): 0x200

=== Component Section ===
FLCOMP   0x09300023
FLILL    0x00000000

--- Details ---
Component 1 density:            4 MB
Component 2 is not used.
Read Clock Frequency:           20 MHz
Read ID and Status Clock Freq.: 33 MHz
Write and Erase Clock Freq.:    33 MHz
Fast Read is supported.
Fast Read Clock Frequency:      33 MHz
No forbidden opcodes.

=== Region Section ===
FLREG0   0x00000000
FLREG1   0x03ff0018
FLREG2   0x00170001
FLREG3   0x00001fff
FLREG4   0x00001fff

--- Details ---
Region 0 (Descr.) 0x00000000 - 0x00000fff
Region 1 (BIOS  ) 0x00018000 - 0x003fffff
Region 2 (ME    ) 0x00001000 - 0x00017fff
Region 3 (GbE   ) is unused.
Region 4 (Platf.) is unused.

=== Master Section ===
FLMSTR1  0xffff0000
FLMSTR2  0xffff0000
FLMSTR3  0x08080118

--- Details ---
      Descr. BIOS ME GbE Platf.
BIOS    rw    rw  rw  rw   rw
ME      rw    rw  rw  rw   rw
GbE                   rw     

checking for opcode 0x03
checking for opcode 0x05
OK.
No board enable found matching coreboot IDs vendor="Sapphire", model="Pure Platinum H61".
The following protocols are supported: FWH, SPI.
Probing for SST SST25VF032B, 4096 kB: page_size=1000
pre-rounding:  start=0x00000000ffc00000, len=0x400000, end=0x0000000100000000
post-rounding: start=0x00000000ffc00000, len=0x400000, end=0x0000000100000000
programmer_map_flash_region: mapping SST25VF032B from 0x00000000ffc00000 to 0x00007efcb8bdf000
RDID returned 0xbf 0x25 0x4a. probe_spi_rdid_generic: id1 0xbf, id2 0x254a
Found SST flash chip "SST25VF032B" (4096 kB, SPI) mapped at physical address 0x00000000ffc00000.
Chip status register is 0x02.
Chip status register: Block Protect Write Disable (BPL) is not set
Chip status register: Auto Address Increment Programming (AAI) is not set
Chip status register: Block Protect 3 (BP3) is not set
Chip status register: Block Protect 2 (BP2) is not set
Chip status register: Block Protect 1 (BP1) is not set
Chip status register: Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is set
Chip status register: Write In Progress (WIP/BUSY) is not set
page_size=1000
pre-rounding:  start=0x00007efcb8bdf000, len=0x400000, end=0x00007efcb8fdf000
post-rounding: start=0x00007efcb8bdf000, len=0x400000, end=0x00007efcb8fdf000
programmer_unmap_flash_region: unmapped 0x00007efcb8bdf000
page_size=1000
pre-rounding:  start=0x00000000ffc00000, len=0x400000, end=0x0000000100000000
post-rounding: start=0x00000000ffc00000, len=0x400000, end=0x0000000100000000
programmer_map_flash_region: mapping SST25VF032B from 0x00000000ffc00000 to 0x00007efcb8bdf000
Block protection is disabled.
coreboot last image size (not ROM size) is 4194304 bytes.
Manufacturer: Sapphire
Mainboard ID: Pure Platinum H61
This coreboot image matches this mainboard.
Reading old flash chip contents... done.
Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EWInvalid OPCODE 0x06, will not execute.
default_spi_write_aai failed during start command execution: -2
Invalid OPCODE 0x04, will not execute.
default_spi_write_aai failed to disable AAI mode.
Reading current flash chip contents... done. Looking for another erase function.
Trying erase function 1... 0x000000-0x007fff:WInvalid OPCODE 0x06, will not execute.
default_spi_write_aai failed during start command execution: -2
Invalid OPCODE 0x04, will not execute.
default_spi_write_aai failed to disable AAI mode.
Reading current flash chip contents... done. Looking for another erase function.
Trying erase function 2... 0x000000-0x00ffff:WInvalid OPCODE 0x06, will not execute.
default_spi_write_aai failed during start command execution: -2
Invalid OPCODE 0x04, will not execute.
default_spi_write_aai failed to disable AAI mode.
Reading current flash chip contents... done. Looking for another erase function.
Trying erase function 3... 0x000000-0x3fffff:EInvalid OPCODE 0x06, will not execute.
spi_chip_erase_60 failed during command execution
Reading current flash chip contents... done. Looking for another erase function.
Trying erase function 4... 0x000000-0x3fffff:EInvalid OPCODE 0x06, will not execute.
spi_chip_erase_c7 failed during command execution
Looking for another erase function.
No usable erase functions left.
FAILED!
Uh oh. Erase/write failed. Checking if anything has changed.
Reading current flash chip contents... done.
Apparently at least some data has changed.
Your flash chip is in an unknown state.
Get help on IRC at chat.freenode.net (channel #flashrom) or
mail flashrom at flashrom.org with the subject "FAILED: <your board name>"!
-------------------------------------------------------------------------------
DO NOT REBOOT OR POWEROFF!
page_size=1000
pre-rounding:  start=0x00007efcb8bdf000, len=0x400000, end=0x00007efcb8fdf000
post-rounding: start=0x00007efcb8bdf000, len=0x400000, end=0x00007efcb8fdf000
programmer_unmap_flash_region: unmapped 0x00007efcb8bdf000
Restoring MMIO space at 0x7efcba6458a0
-------------- next part --------------
flashrom v0.9.9-r1954 on Linux 4.12.0-1-amd64 (x86_64)
flashrom is free software, get the source code at https://flashrom.org

flashrom was built with libpci 3.5.2, GCC 6.3.0 20170221, little endian
Command line (7 args): flashrom -VVV -p internal:ich_spi_mode=hwseq -c SST25VF032B -w build/coreboot.rom
Calibrating delay loop... OS timer resolution is 1 usecs, 3875M loops per second, 10 myus = 10 us, 100 myus = 117 us, 1000 myus = 1013 us, 10000 myus = 9978 us, 4 myus = 4 us, OK.
Initializing internal programmer
Found candidate at: 00000500-00000510
Found coreboot table at 0x00000500.
Found candidate at: 00000000-00000908
Found coreboot table at 0x00000000.
coreboot table found at 0x7fedd000.
coreboot header(24) checksum: fa8a table(2312) checksum: 6aa1 entries: 30
Vendor ID: Sapphire, part ID: Pure Platinum H61
Using Internal DMI decoder.
page_size=1000
pre-rounding:  start=0x00000000000f0000, len=0x10000, end=0x0000000000100000
post-rounding: start=0x00000000000f0000, len=0x10000, end=0x0000000000100000
page_size=1000
pre-rounding:  start=0x000000007fea7020, len=0x212, end=0x000000007fea7232
post-rounding: start=0x000000007fea7000, len=0x1000, end=0x000000007fea8000
DMI string chassis-type: "Desktop"
page_size=1000
pre-rounding:  start=0x00007efd3063f020, len=0x212, end=0x00007efd3063f232
post-rounding: start=0x00007efd3063f000, len=0x1000, end=0x00007efd30640000
page_size=1000
pre-rounding:  start=0x00007efd30640000, len=0x10000, end=0x00007efd30650000
post-rounding: start=0x00007efd30640000, len=0x10000, end=0x00007efd30650000
DMI string system-manufacturer: "Sapphire"
DMI string system-product-name: "Pure Platinum H61"
DMI string system-version: "1.0"
DMI string baseboard-manufacturer: "Sapphire"
DMI string baseboard-product-name: "Pure Platinum H61"
DMI string baseboard-version: "1.0"
Found chipset "Intel H61" with PCI ID 8086:1c5c.
Enabling flash write... Root Complex Register Block address = 0xfed1c000
page_size=1000
pre-rounding:  start=0x00000000fed1c000, len=0x4000, end=0x00000000fed20000
post-rounding: start=0x00000000fed1c000, len=0x4000, end=0x00000000fed20000
GCS = 0xc21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI)
Top Swap: enabled (A16(+) inverted)
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode enabled
0xffe00000/0xffa00000 FWH decode enabled
0xffd80000/0xff980000 FWH decode enabled
0xffd00000/0xff900000 FWH decode enabled
0xffc80000/0xff880000 FWH decode enabled
0xffc00000/0xff800000 FWH decode enabled
0xff700000/0xff300000 FWH decode enabled
0xff600000/0xff200000 FWH decode enabled
0xff500000/0xff100000 FWH decode enabled
0xff400000/0xff000000 FWH decode enabled
Maximum FWH chip size: 0x100000 bytes
SPI Read Configuration: prefetching enabled, caching enabled, 
BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled
SPIBAR = 0x00007efd3064c000 + 0x3800
user selected hwseq
0x04: 0xc008 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=0, FDV=1, FLOCKDN=1
Warning: SPI Configuration Lockdown activated.
The Flash Descriptor Override Strap-Pin is set. Restrictions implied by
the Master Section of the flash descriptor are NOT in effect. Please note
that Protected Range (PR) restrictions still apply.
Reading OPCODES... done
        OP        Type      Pre-OP
op[0]: 0x01, write w/o addr, none
op[1]: 0x02, write w/  addr, none
op[2]: 0x03, read  w/  addr, none
op[3]: 0x05, read  w/o addr, none
op[4]: 0x20, write w/  addr, none
op[5]: 0x9f, read  w/o addr, none
op[6]: 0xd8, write w/  addr, none
op[7]: 0x0b, read  w/  addr, none
Pre-OP 0: 0x06, Pre-OP 1: 0x50
0x06: 0x0000 (HSFC)
HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0
0x08: 0x003fffc0 (FADDR)
0x50: 0x0000ffff (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write.
0x58: 0x03ff0018 FREG1: BIOS region (0x00018000-0x003fffff) is read-write.
0x5C: 0x00170001 FREG2: Management Engine region (0x00001000-0x00017fff) is read-write.
0x60: 0x00001fff FREG3: Gigabit Ethernet region is unused.
0x64: 0x00001fff FREG4: Platform Data region is unused.
0x74: 0x00000000 (PR0 is unused)
0x78: 0x00000000 (PR1 is unused)
0x7C: 0x00000000 (PR2 is unused)
0x80: 0x00000000 (PR3 is unused)
0x84: 0x00000000 (PR4 is unused)
0x90: 0x84 (SSFS)
SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0
0x91: 0xf97f20 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=2, DBC=63, SME=0, SCF=1
0x94: 0x5006     (PREOP)
0x96: 0xb32d     (OPTYPE)
0x98: 0x05030201 (OPMENU)
0x9C: 0x0bd89f20 (OPMENU+4)
0xA0: 0x00000000 (BBAR)
0xC4: 0x00802009 (LVSCC)
LVSCC: BES=0x1, WG=0, WSR=1, WEWS=0, EO=0x20, VCL=1
0xC8: 0x00002009 (UVSCC)
UVSCC: BES=0x1, WG=0, WSR=1, WEWS=0, EO=0x20
0xD0: 0x00000000 (FPB)
Reading flash descriptors mapped by the chipset via FDOC/FDOD... done.
=== Content Section ===
FLVALSIG 0x0ff0a55a
FLMAP0   0x02040003
FLMAP1   0x12100206
FLMAP2   0x00210120

--- Details ---
NR          (Number of Regions):                     3
FRBA        (Flash Region Base Address):         0x040
NC          (Number of Components):                  1
FCBA        (Flash Component Base Address):      0x030
ISL         (ICH/PCH Strap Length):                 18
FISBA/FPSBA (Flash ICH/PCH Strap Base Address):  0x100
NM          (Number of Masters):                     3
FMBA        (Flash Master Base Address):         0x060
MSL/PSL     (MCH/PROC Strap Length):                 1
FMSBA       (Flash MCH/PROC Strap Base Address): 0x200

=== Component Section ===
FLCOMP   0x09300023
FLILL    0x00000000

--- Details ---
Component 1 density:            4 MB
Component 2 is not used.
Read Clock Frequency:           20 MHz
Read ID and Status Clock Freq.: 33 MHz
Write and Erase Clock Freq.:    33 MHz
Fast Read is supported.
Fast Read Clock Frequency:      33 MHz
No forbidden opcodes.

=== Region Section ===
FLREG0   0x00000000
FLREG1   0x03ff0018
FLREG2   0x00170001
FLREG3   0x00001fff
FLREG4   0x00001fff

--- Details ---
Region 0 (Descr.) 0x00000000 - 0x00000fff
Region 1 (BIOS  ) 0x00018000 - 0x003fffff
Region 2 (ME    ) 0x00001000 - 0x00017fff
Region 3 (GbE   ) is unused.
Region 4 (Platf.) is unused.

=== Master Section ===
FLMSTR1  0xffff0000
FLMSTR2  0xffff0000
FLMSTR3  0x08080118

--- Details ---
      Descr. BIOS ME GbE Platf.
BIOS    rw    rw  rw  rw   rw
ME      rw    rw  rw  rw   rw
GbE                   rw     

OK.
No board enable found matching coreboot IDs vendor="Sapphire", model="Pure Platinum H61".
The following protocols are supported: FWH, Programmer-specific.
No EEPROM/flash device found.
Note: flashrom can never write if the flash chip isn't found automatically.
Restoring MMIO space at 0x7efd3064f8a0


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