[flashrom] [PATCH 2/3] Add support for GD25D05B and GD25D10B

Hatim Kanchwala hatim at hatimak.me
Wed Mar 16 16:35:02 CET 2016


On Saturday 12 March 2016 09:05 AM, Stefan Tauner wrote:
> On Sat, 12 Mar 2016 02:33:14 +0530
> Hatim Kanchwala <hatim at hatimak.me> wrote:
> 
>> Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
>> ---
>>  flashchips.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>>  flashchips.h |  4 ++--
>>  2 files changed, 78 insertions(+), 2 deletions(-)
>>
>> diff --git a/flashchips.c b/flashchips.c
>> index 5da56d0..a76192c 100644
>> --- a/flashchips.c
>> +++ b/flashchips.c
>> @@ -5628,30 +5628,106 @@ const struct flashchip flashchips[] = {
>>  					{16 * 1024, 1},
>>  				},
>>  				.block_erase = erase_block_jedec,
>>  			}, {
>>  				.eraseblocks = { {2048 * 1024, 1} },
>>  				.block_erase = erase_chip_block_jedec,
>>  			},
>>  		},
>>  		.write		= write_jedec_1, /* Supports a fast mode too */
>>  		.read		= read_memmapped,
>>  		.voltage	= {3000, 3600}, /* 3.0-3.6V for type -70, others 2.7-3.6V */
>>  	},
>>  
>>  	{
>>  		.vendor		= "GigaDevice",
>> +		.name		= "GD25D05B",
>> +		.bustype	= BUS_SPI,
>> +		.manufacture_id	= GIGADEVICE_ID,
>> +		.model_id	= GIGADEVICE_GD25Q512,
>> +		.total_size	= 64,
>> +		.page_size	= 256,
>> +		.feature_bits	= FEATURE_WRSR_WREN,
>> +		.tested		= TEST_OK_PREW,
>> +		.probe		= probe_spi_rdid,
>> +		.probe_timing	= TIMING_ZERO,
>> +		.block_erasers	=
>> +		{
>> +			{
>> +				.eraseblocks = { {4 * 1024, 16} },
>> +				.block_erase = spi_block_erase_20,
>> +			}, {
>> +				.eraseblocks = { {32 * 1024, 2} },
>> +				.block_erase = spi_block_erase_52,
>> +			}, {
>> +				.eraseblocks = { {64 * 1024, 1} },
>> +				.block_erase = spi_block_erase_d8,
>> +			}, {
> 
> Can you please test if this really exists? In the Q05 datasheet it is
> explicitly stated that there is no 64k block erase. This is missing the
> D05B datasheet I am looking at but that be an error in the datasheet.
> Since you have the chip at hand, real testing would be appreciated - it
> does not matter that much though.

There is no Q05, it is Q512. The datasheet I am referring to does mention the 64kB block erase (http://www.gigadevice.com/product/download/185.html?locale=en_US). And the D05B datasheet also mentions the 64kB block erase (http://www.gigadevice.com/product/download/401.html?locale=en_US). Nevertheless, real testing confirms 64kB block erase (logs attached).

> 
>> +				.eraseblocks = { {64 * 1024, 1} },
>> +				.block_erase = spi_block_erase_60,
>> +			}, {
>> +				.eraseblocks = { {64 * 1024, 1} },
>> +				.block_erase = spi_block_erase_c7,
>> +			}
>> +		},
>> +		.printlock	= spi_prettyprint_status_register_bp2_srwd,
>> +		.unlock		= spi_disable_blockprotect_bp2_srwd,
>> +		.write		= spi_chip_write_256,
>> +		.read		= spi_chip_read, /* Fast read (0x0B) supported */
> 
> Should be
> 		.read		= spi_chip_read, /* Fast read (0x0B), dual I/O supported */
> AFAICS.
> 

Yes, my bad. The D has dual I/O but the Q has quad as well. Newer patch follows in a separate successive mail. Thanks.

>> +		.voltage	= {2700, 3600},
>> +	},
>> +
>> +	{
>> +		.vendor		= "GigaDevice",
>> +		.name		= "GD25D10B",
>> +		.bustype	= BUS_SPI,
>> +		.manufacture_id	= GIGADEVICE_ID,
>> +		.model_id	= GIGADEVICE_GD25Q10,
>> +		.total_size	= 128,
>> +		.page_size	= 256,
>> +		.feature_bits	= FEATURE_WRSR_WREN,
>> +		.tested		= TEST_OK_PREW,
>> +		.probe		= probe_spi_rdid,
>> +		.probe_timing	= TIMING_ZERO,
>> +		.block_erasers	=
>> +		{
>> +			{
>> +				.eraseblocks = { {4 * 1024, 32} },
>> +				.block_erase = spi_block_erase_20,
>> +			}, {
>> +				.eraseblocks = { {32 * 1024, 4} },
>> +				.block_erase = spi_block_erase_52,
>> +			}, {
>> +				.eraseblocks = { {64 * 1024, 2} },
>> +				.block_erase = spi_block_erase_d8,
>> +			}, {
>> +				.eraseblocks = { {128 * 1024, 1} },
>> +				.block_erase = spi_block_erase_60,
>> +			}, {
>> +				.eraseblocks = { {128 * 1024, 1} },
>> +				.block_erase = spi_block_erase_c7,
>> +			}
>> +		},
>> +		.printlock	= spi_prettyprint_status_register_bp2_srwd,
>> +		.unlock		= spi_disable_blockprotect_bp2_srwd,
>> +		.write		= spi_chip_write_256,
>> +		.read		= spi_chip_read, /* Fast read (0x0B) supported */
> 
> Should be
> 		.read		= spi_chip_read, /* Fast read (0x0B), dual I/O supported */
> AFAICS.
> 
>> +		.voltage	= {2700, 3600},
>> +	},
>> +
>> +	{
>> +		.vendor		= "GigaDevice",
>>  		.name		= "GD25LQ10B",
>>  		.bustype	= BUS_SPI,
>>  		.manufacture_id	= GIGADEVICE_ID,
>>  		.model_id	= GIGADEVICE_GD25LQ10,
>>  		.total_size	= 128,
>>  		.page_size	= 256,
>>  		/* Supports SFDP */
>>  		/* OTP: 1536B total; read 0x48; write 0x42, erase 0x44 */
>>  		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
>>  		.tested		= TEST_OK_PREW,
>>  		.probe		= probe_spi_rdid,
>>  		.probe_timing	= TIMING_ZERO,
>>  		.block_erasers	=
>>  		{
>>  			{
>> diff --git a/flashchips.h b/flashchips.h
>> index 3e2b18c..a2d25ec 100644
>> --- a/flashchips.h
>> +++ b/flashchips.h
>> @@ -351,32 +351,32 @@
>>  #define FUJITSU_MBM29LV004TC	0xB5
>>  #define FUJITSU_MBM29LV008BA	0x37
>>  #define FUJITSU_MBM29LV008TA	0x3E
>>  #define FUJITSU_MBM29LV080A	0x38
>>  #define FUJITSU_MBM29LV200BC	0xBF
>>  #define FUJITSU_MBM29LV200TC	0x3B
>>  #define FUJITSU_MBM29LV400BC	0xBA
>>  #define FUJITSU_MBM29LV400TC	0xB9
>>  #define FUJITSU_MBM29LV800BA	0x5B	/* Same as MBM29LV800BE */
>>  #define FUJITSU_MBM29LV800TA	0xDA	/* Same as MBM29LV800TE */
>>  #define FUJITSU_MBM29LV160BE	0x49	/* 16 b mode 0x2249 */
>>  #define FUJITSU_MBM29LV160TE	0xC4	/* 16 b mode 0x22C4 */
>>  
>>  #define GIGADEVICE_ID		0xC8	/* GigaDevice */
>>  #define GIGADEVICE_GD25T80	0x3114
>> -#define GIGADEVICE_GD25Q512	0x4010
>> -#define GIGADEVICE_GD25Q10	0x4011
>> +#define GIGADEVICE_GD25Q512	0x4010	/* Same as GD25D05B */
>> +#define GIGADEVICE_GD25Q10	0x4011	/* Same as GD25D10B */
> 
> Ways to distinguish them should be noted here. Probably the best way is
> to read the second status register of the Q10 that is not present in
> the D10B versions.
> 

Agreed.

>>  #define GIGADEVICE_GD25Q20	0x4012	/* Same as GD25QB */
>>  #define GIGADEVICE_GD25Q40	0x4013	/* Same as GD25QB */
>>  #define GIGADEVICE_GD25Q80	0x4014	/* Same as GD25Q80B (which has OTP) */
>>  #define GIGADEVICE_GD25Q16	0x4015	/* Same as GD25Q16B (which has OTP) */
>>  #define GIGADEVICE_GD25Q32	0x4016	/* Same as GD25Q32B */
>>  #define GIGADEVICE_GD25Q64	0x4017	/* Same as GD25Q64B */
>>  #define GIGADEVICE_GD25Q128	0x4018	/* GD25Q128B and GD25Q128C only, can be distinguished by SFDP */
>>  #define GIGADEVICE_GD25VQ21B	0x4212
>>  #define GIGADEVICE_GD25VQ41B	0x4213  /* Same as GD25VQ40C, can be distinguished by SFDP */
>>  #define GIGADEVICE_GD25VQ80C	0x4214
>>  #define GIGADEVICE_GD25VQ16C	0x4215
>>  #define GIGADEVICE_GD25LQ10	0x6011	/* Same as GD25LQ10B, can be distinguished by SFDP */
>>  #define GIGADEVICE_GD25LQ20	0x6012	/* Same as GD25LQ20B, can be distinguished by SFDP */
>>  #define GIGADEVICE_GD25LQ40	0x6013	/* Same as GD25LQ40B, can be distinguished by SFDP */
>>  #define GIGADEVICE_GD25LQ80	0x6014	/* Same as GD25LQ80B, can be distinguished by SFDP */
> 
> 

-- 
Kind Regards,
Hatim Kanchwala
http://hatimak.me
B. Tech. Electrical Engineering
Indian Institute of Technology Patna
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