[flashrom] [PATCH 3/6] WIP: Add support for status register infrastructure to existing chips
Hatim Kanchwala
hatim at hatimak.me
Tue Jul 5 22:28:02 CEST 2016
- struct status_register defines added for the following chips (66 in total) -
- AMIC(4) : A25L080, A25LQ16, A25LQ32A, A25L032
- Macronix(15) : MX25L6408E, MX25L6406E, MX25L1605D, MX25L3205D, MX25L6405D, MX25L1608D, MX25L3208D, MX25L6408D, MX25L6436E, MX25L6445E, MX25L6465E, MX25L12865E, MX25L12845E, MX25L12835F, MX25L1673E
- GigaDevice(41) : GD25LQ16, GD25LQ40, GD25LQ80B, GD25LQ40B, GD25LQ64C, GD25LQ80, GD25LQ128C, GD25LQ32C, GD25LQ16, GD25LQ40, GD25LQ80B, GD25LQ40B, GD25LQ64C, GD25LQ80, GD25LQ128C, GD25LQ32C, GD25Q16B, GD25Q32B, GD25Q64B, GD25Q10, GD25Q16, GD25Q20, GD25Q40, GD25Q80, GD25VQ16C, GD25VQ80C, GD25Q16C, GD25Q40C, GD25VQ21B, GD25VQ41B, GD25Q21B, GD25Q41B, GD25Q80B, GD25Q128, GD25LQ05B, GD25LQ10B, GD25LQ20B, GD25Q32C, GD25Q64C, GD25Q127C, GD25Q128C
- Winbond(6) : W25Q80, W25Q16, W25Q32, W25Q40BL, W25Q64FV, W25Q128FW
- 16 of the above support new infrastructure (in flashchips.c) (WIP)
- 19 unique struct definitions were required to represent all of the above chips.
- Note that quite a few chips don't have support in flashrom (yet).
Signed-off-by: Hatim Kanchwala <hatim at hatimak.me>
---
Makefile | 2 +-
flashchips.c | 169 +++++++++++++++++++++++----
spi25_statusreg.h | 36 ++++++
statusreg_layouts.c | 320 ++++++++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 505 insertions(+), 22 deletions(-)
create mode 100644 statusreg_layouts.c
diff --git a/Makefile b/Makefile
index de08492..ed4979e 100644
--- a/Makefile
+++ b/Makefile
@@ -504,27 +504,27 @@ endif
ifeq ($(CONFIG_IT8212), yes)
UNSUPPORTED_FEATURES += CONFIG_IT8212=yes
else
override CONFIG_IT8212 = no
endif
endif
###############################################################################
# Flash chip drivers and bus support infrastructure.
CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \
sst28sf040.o 82802ab.o \
sst49lfxxxc.o sst_fwhub.o flashchips.o spi.o spi25.o spi25_statusreg.o \
- writeprotect.o opaque.o sfdp.o en29lv640b.o at45db.o
+ writeprotect.o statusreg_layouts.o opaque.o sfdp.o en29lv640b.o at45db.o
###############################################################################
# Library code.
LIB_OBJS = layout.o flashrom.o udelay.o programmer.o helpers.o
###############################################################################
# Frontend related stuff.
CLI_OBJS = cli_classic.o cli_output.o cli_common.o print.o
# Set the flashrom version string from the highest revision number of the checked out flashrom files.
# Note to packagers: Any tree exported with "make export" or "make tarball"
diff --git a/flashchips.c b/flashchips.c
index 40b6b8e..0afd297 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -15,26 +15,27 @@
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "flash.h"
#include "flashchips.h"
#include "chipdrivers.h"
+#include "spi25_statusreg.h"
/**
* List of supported flash chips.
*
* Please keep the list sorted by vendor name and chip family, so that the output of 'flashrom -L' is roughly
* alphabetically sorted. Within families keep them in order of density.
*/
const struct flashchip flashchips[] = {
/*
* .vendor = Vendor name
* .name = Chip name
* .bustype = Supported flash bus types (Parallel, LPC...)
@@ -1155,27 +1156,28 @@ const struct flashchip flashchips[] = {
.block_erasers =
{
{
.eraseblocks = { { 4 * 1024, 256 } },
.block_erase = spi_block_erase_20,
}, {
.eraseblocks = { { 64 * 1024, 16 } },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { { 1024 * 1024, 1 } },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_bp2_srwd,
+ /* TODO: Read/write 2nd status register */
+ .status_register = &a25l080_sr,
.unlock = spi_disable_blockprotect,
.write = spi_chip_write_256,
.read = spi_chip_read,
.voltage = {2700, 3600},
},
{
.vendor = "AMIC",
.name = "A25L016",
.bustype = BUS_SPI,
.manufacture_id = AMIC_ID_NOPREFIX,
.model_id = AMIC_A25L016,
.total_size = 2048,
@@ -1265,36 +1267,37 @@ const struct flashchip flashchips[] = {
.eraseblocks = { { 64 * 1024, 32 } },
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { { 64 * 1024, 32 } },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { { 2048 * 1024, 1 } },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { { 2048 * 1024, 1 } },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_amic_a25l032, /* bit5: T/B, bit6: prot size */
- .unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: 2nd status reg (read with 0x35) */
+ /* TODO: Read/write 2nd status register */
+ .status_register = &a25lq16_32a_sr,
+ .unlock = spi_disable_blockprotect_bp2_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read,
.voltage = {2700, 3600},
},
{
.vendor = "AMIC",
- .name = "A25LQ032/A25LQ32A",
+ .name = "A25LQ032",
.bustype = BUS_SPI,
.manufacture_id = AMIC_ID_NOPREFIX,
.model_id = AMIC_A25LQ032,
.total_size = 4096,
.page_size = 256,
/* A25LQ32A supports SFDP */
/* OTP: 64B total; read 0x4B, 0x48; write 0x42 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
.tested = TEST_UNTESTED,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
@@ -1305,27 +1308,68 @@ const struct flashchip flashchips[] = {
.eraseblocks = { { 64 * 1024, 64 } },
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { { 64 * 1024, 64 } },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { { 4096 * 1024, 1 } },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { { 4096 * 1024, 1 } },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_amic_a25l032, /* bit5: T/B, bit6: prot size */
+ /* TODO: Read/write 2nd status register */
+ .status_register = &a25l032_sr,
+ .unlock = spi_disable_blockprotect_bp2_srwd,
+ .write = spi_chip_write_256,
+ .read = spi_chip_read,
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "AMIC",
+ .name = "A25LQ32A",
+ .bustype = BUS_SPI,
+ .manufacture_id = AMIC_ID_NOPREFIX,
+ .model_id = AMIC_A25LQ032,
+ .total_size = 4096,
+ .page_size = 256,
+ /* A25LQ32A supports SFDP */
+ /* OTP: 64B total; read 0x4B, 0x48; write 0x42 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .tested = TEST_UNTESTED,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { { 4 * 1024, 1024 } },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { { 64 * 1024, 64 } },
+ .block_erase = spi_block_erase_52,
+ }, {
+ .eraseblocks = { { 64 * 1024, 64 } },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { { 4096 * 1024, 1 } },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { { 4096 * 1024, 1 } },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ .status_register = &a25lq16_32a_sr,
.unlock = spi_disable_blockprotect_bp2_srwd, /* TODO: 2nd status reg (read with 0x35) */
.write = spi_chip_write_256,
.read = spi_chip_read,
.voltage = {2700, 3600},
},
{
.vendor = "AMIC",
.name = "A25LQ64",
.bustype = BUS_SPI,
.manufacture_id = AMIC_ID_NOPREFIX,
.model_id = AMIC_A25LQ64,
.total_size = 8192,
@@ -5660,28 +5704,29 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {32 * 1024, 16} },
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {64 * 1024, 8} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {512 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {512 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_bp4_srwd,
- .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */
+ /* TODO: Read/write 2nd status register */
+ .status_register = &gd25lq_sr,
+ .unlock = spi_disable_blockprotect_bp4_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1695, 1950},
},
{
.vendor = "GigaDevice",
.name = "GD25LQ80",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25LQ80,
.total_size = 1024,
.page_size = 256,
@@ -5699,28 +5744,29 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {32 * 1024, 32} },
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {64 * 1024, 16} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {1 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {1 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_bp4_srwd,
- .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */
+ /* TODO: Read/write 2nd status register*/
+ .status_register = &gd25lq_sr,
+ .unlock = spi_disable_blockprotect_bp4_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1695, 1950},
},
{
.vendor = "GigaDevice",
.name = "GD25LQ16",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25LQ16,
.total_size = 2048,
.page_size = 256,
@@ -5738,28 +5784,29 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {32 * 1024, 64} },
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {64 * 1024, 32} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {2 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {2 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_bp4_srwd,
- .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */
+ /* TODO: Read/write 2nd status register */
+ .status_register = &gd25lq_sr,
+ .unlock = spi_disable_blockprotect_bp4_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1695, 1950},
},
{
.vendor = "GigaDevice",
.name = "GD25LQ32",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25LQ32,
.total_size = 4096,
.page_size = 256,
@@ -6050,27 +6097,66 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
.printlock = spi_prettyprint_status_register_bp4_srwd,
.unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
},
{
.vendor = "GigaDevice",
- .name = "GD25Q16(B)",
+ .name = "GD25Q16",
+ .bustype = BUS_SPI,
+ .manufacture_id = GIGADEVICE_ID,
+ .model_id = GIGADEVICE_GD25Q16,
+ .total_size = 2048,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_WREN,
+ .tested = TEST_OK_PREW,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 512} },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 64} },
+ .block_erase = spi_block_erase_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 32} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {2 * 1024 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { {2 * 1024 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ }
+ },
+ /* TODO: Read/write 2nd status register */
+ .status_register = &gd25q10_20_40_80_sr,
+ .unlock = spi_disable_blockprotect_bp4_srwd,
+ .write = spi_chip_write_256,
+ .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "GigaDevice",
+ .name = "GD25Q16B",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25Q16,
.total_size = 2048,
.page_size = 256,
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 (B version only) */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
@@ -6080,28 +6166,29 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {32 * 1024, 64} },
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {64 * 1024, 32} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {2 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {2 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_bp4_srwd,
- .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */
+ /* TODO: Read/write 2nd status register */
+ .status_register = &gd25q16_32_64b_sr,
+ .unlock = spi_disable_blockprotect_bp4_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
},
{
.vendor = "GigaDevice",
.name = "GD25Q32(B)",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25Q32,
.total_size = 4096,
.page_size = 256,
@@ -7515,53 +7602,88 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {2 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
},
},
.printlock = spi_prettyprint_status_register_bp3_srwd, /* MX25L1605A bp2 only */
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) supported (MX25L1608E supports dual-I/O read) */
.voltage = {2700, 3600},
},
{
.vendor = "Macronix",
- .name = "MX25L1605D/MX25L1608D/MX25L1673E",
+ .name = "MX25L1605D/MX25L1608D",
+ .bustype = BUS_SPI,
+ .manufacture_id = MACRONIX_ID,
+ .model_id = MACRONIX_MX25L1605,
+ .total_size = 2048,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_WREN,
+ .tested = TEST_OK_PREW,
+ .probe = probe_spi_rdid,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 512} },
+ .block_erase = spi_block_erase_20,
+ }, {
+ .eraseblocks = { {64 * 1024, 32} },
+ .block_erase = spi_block_erase_d8,
+ }, {
+ .eraseblocks = { {2 * 1024 * 1024, 1} },
+ .block_erase = spi_block_erase_60,
+ }, {
+ .eraseblocks = { {2 * 1024 * 1024, 1} },
+ .block_erase = spi_block_erase_c7,
+ },
+ },
+ .status_register = &mx25lx5d_sr,
+ .unlock = spi_disable_blockprotect_bp3_srwd,
+ .write = spi_chip_write_256,
+ .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "Macronix",
+ .name = "MX25L1673E",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L1605,
.total_size = 2048,
.page_size = 256,
.feature_bits = FEATURE_WRSR_WREN,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 512} },
.block_erase = spi_block_erase_20,
}, {
.eraseblocks = { {64 * 1024, 32} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {2 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {2 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
},
},
- .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: Continuously Program (CP) mode, for 73E is quad enable */
+ .status_register = &mx25lx65e_sr,
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */
.voltage = {2700, 3600},
},
{
.vendor = "Macronix",
.name = "MX25L1635D",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L1635D,
.total_size = 2048,
@@ -7684,27 +7806,27 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {4 * 1024, 1024} },
.block_erase = spi_block_erase_20,
}, {
.eraseblocks = { {64 * 1024, 64} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {4 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {4 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
},
},
- .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: continuously program mode */
+ .status_register = &mx25lx5d_sr,
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */
.voltage = {2700, 3600},
},
{
.vendor = "Macronix",
.name = "MX25L3206E/MX25L3208E",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L3205,
.total_size = 4096,
@@ -7870,27 +7992,27 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {4 * 1024, 2048} },
.block_erase = spi_block_erase_20,
}, {
.eraseblocks = { {64 * 1024, 128} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: continuously program mode */
+ .status_register = &mx25lx5d_sr,
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B), dual I/O read (0xBB) supported */
.voltage = {2700, 3600},
},
{
.vendor = "Macronix",
.name = "MX25L6406E/MX25L6408E",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L6405,
.total_size = 8192,
@@ -7910,27 +8032,27 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {64 * 1024, 128} },
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {64 * 1024, 128} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_bp3_srwd,
+ .status_register = &mx25l64xe_sr,
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B), dual I/O read supported */
.voltage = {2700, 3600},
},
{
.vendor = "Macronix",
.name = "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L6405,
.total_size = 8192,
@@ -7950,27 +8072,32 @@ const struct flashchip flashchips[] = {
.eraseblocks = { {32 * 1024, 256} },
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {64 * 1024, 128} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {8 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
- .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
+ /* FIXME: MX25L6473E has an additional configuration register (which behaves like
+ * a 2nd status register).
+ * FIXME: Datasheet for MX25L6473E indicates bit 7 is RESV (instead
+ * of SRWD), but similar chips have SRWD.
+ */
+ .status_register = &mx25lx65e_sr,
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
},
{
.vendor = "Macronix",
.name = "MX25L12805D",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L12805D,
.total_size = 16384,
@@ -8026,27 +8153,27 @@ const struct flashchip flashchips[] = {
.block_erase = spi_block_erase_52,
}, {
.eraseblocks = { {64 * 1024, 256} },
.block_erase = spi_block_erase_d8,
}, {
.eraseblocks = { {16 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_60,
}, {
.eraseblocks = { {16 * 1024 * 1024, 1} },
.block_erase = spi_block_erase_c7,
}
},
/* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */
- .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
+ .status_register = &mx25lx65e_sr,
.unlock = spi_disable_blockprotect_bp3_srwd,
.write = spi_chip_write_256,
.read = spi_chip_read, /* Fast read (0x0B) supported */
.voltage = {2700, 3600},
},
{
.vendor = "Macronix",
.name = "MX25U1635E",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25U1635E,
.total_size = 2048,
diff --git a/spi25_statusreg.h b/spi25_statusreg.h
index b082f45..8bfffa0 100644
--- a/spi25_statusreg.h
+++ b/spi25_statusreg.h
@@ -66,14 +66,50 @@ enum wp_mode {
/* Status register is protected and can not be written to until next
* power down/up cycle, post which status register will be unlocked
* and can be written to after a WREN. */
WP_MODE_POWER_CYCLE,
/* Status register is permanently protected and cannot be written to. */
WP_MODE_PERMANENT,
};
/* Describes corresponding bits from enum status_register_bit */
extern char *statreg_bit_desc[][2];
+/* === Single status register === */
+/* === AMIC === */
+extern struct status_register a25l080_sr;
+
+/* === Macronix === */
+extern struct status_register mx25l64xe_sr;
+extern struct status_register mx25lx5d_sr;
+extern struct status_register mx25lx65e_sr;
+
+/* === Double status registers === */
+/* === AMIC === */
+extern struct status_register a25lq16_32a_sr;
+extern struct status_register a25l032_sr;
+
+/* === GigaDevice === */
+extern struct status_register gd25lq_sr;
+extern struct status_register gd25q16_32_64b_sr;
+extern struct status_register gd25q10_20_40_80_sr;
+extern struct status_register gd25vq16_80c_q16_40c_sr;
+extern struct status_register gd25vq21_41b_q21_q41b_sr;
+extern struct status_register gd25q80b_128_sr;
+
+/* === Winbond === */
+extern struct status_register w25q80_16_32_sr;
+extern struct status_register w25q40bl_64fv_sr;
+
+/* === Triple status registers === */
+/* === GigaDevice === */
+extern struct status_register gd25lq05_10_20b_sr;
+extern struct status_register gd25q32_64c_sr;
+extern struct status_register gd25q127c_sr;
+extern struct status_register gd25q128c_sr;
+
+/* === Winbond === */
+extern struct status_register w25q128fw_sr;
+
#endif /* !__SPI25_STATUSREG_H__ */
diff --git a/statusreg_layouts.c b/statusreg_layouts.c
new file mode 100644
index 0000000..f4275af
--- /dev/null
+++ b/statusreg_layouts.c
@@ -0,0 +1,320 @@
+/*
+ * This file is part of the flashrom project.
+ *
+ * Copyright (C) 2016 Hatim Kanchwala <hatim at hatimak.me>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "chipdrivers.h"
+#include "flash.h"
+#include "spi25_statusreg.h"
+
+/*
+ * struct status_register {
+ * enum status_register_bit layout[MAX_STATUS_REGISTERS + 1][8];
+ * uint8_t (*read) (struct flashctx *flash, enum status_register_num SRn);
+ * int (*write) (struct flashctx *flash, enum status_register_num SRn, uint8_t status);
+ * int (*print) (struct flashctx *flash, enum status_register_num SRn);
+ * enum wp_mode (*get_wp_mode) (struct flashctx *flash);
+ * int (*set_wp_mode) (struct flashctx *flash, enum wp_mode wp_mode);
+ * int (*print_wp_mode) (struct flashctx *flash);
+ * };
+ */
+
+/* === Single status register === */
+/* === AMIC === */
+/* A25L080 */
+struct status_register a25l080_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, RESV, RESV, SRP0 },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+/* === Macronix === */
+/* MX25L6408E, MX25L6406E */
+struct status_register mx25l64xe_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, RESV, SRP0 },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* MX25L1605D, MX25L3205D, MX25L6405D, MX25L1608D, MX25L3208D,
+ * MX25L6408D */
+// TODO(hatim): Add support for MX25L6408D
+struct status_register mx25lx5d_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, CP, SRP0 },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* MX25L6436E, MX25L6445E, MX25L6465E, MX25L12865E, MX25L12845E,
+ * MX25L12835F, MX25L1673E
+ * FIXME: MX25L12845E, MX25L12835F (These two chips have
+ * a configuration register that behaves like a 2nd status
+ * register.)
+ */
+struct status_register mx25lx65e_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, QE, SRP0 },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* === Double status registers === */
+/* === AMIC === */
+/* A25LQ16, A25LQ32A */
+struct status_register a25lq16_32a_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, TB, SEC, SRP0 },
+ { SRP1, QE, APT, RESV, RESV, RESV, CMP, SUS },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* A25L032 */
+struct status_register a25l032_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, TB, SEC, SRP0 },
+ { SRP1, RESV, APT, RESV, RESV, RESV, CMP, RESV },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* === GigaDevice === */
+/* GD25LQ16, GD25LQ40, GD25LQ80B, GD25LQ40B, GD25LQ64C, GD25LQ80,
+ * GD25LQ128C, GD25LQ32C */
+// TODO(hatim): Add support for GD25LQ32C, GD25LQ80B, GD25LQ40B, GD25LQ64C, GD25LQ32C
+struct status_register gd25lq_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { SRP1, QE, SUS2, LB1, LB2, LB3, CMP, SUS1 },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* GD25Q16B, GD25Q32B, GD25Q64B */
+struct status_register gd25q16_32_64b_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { RESV, QE, LB1, RESV, RESV, RESV, CMP, SUS },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* GD25Q10, GD25Q16, GD25Q20, GD25Q40, GD25Q80 */
+struct status_register gd25q10_20_40_80_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { SRP1, QE, RESV, RESV, RESV, RESV, RESV, RESV },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* GD25VQ16C, GD25VQ80C, GD25Q16C, GD25Q40C */
+struct status_register gd25vq16_80c_q16_40c_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { SRP1, QE, LB1, RESV, RESV, HPF, CMP, SUS },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* GD25VQ21B, GD25VQ41B, GD25Q21B, GD25Q41B */
+struct status_register gd25vq21_41b_q21_q41b_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { SRP1, QE, HPF, LB1, LB2, LB3, CMP, SUS },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* GD25Q80B, GD25Q128 */
+struct status_register gd25q80b_128_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { SRP1, QE, LB1, RESV, RESV, RESV, CMP, SUS },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* === Winbond === */
+/* W25Q80, W25Q16, W25Q32 */
+struct status_register w25q80_16_32_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, TB, SEC, SRP0 },
+ { SRP1, QE, RESV, RESV, RESV, RESV, RESV, RESV },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* W25Q40BL, W25Q64FV */
+struct status_register w25q40bl_64fv_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, TB, SEC, SRP0 },
+ { SRP1, QE, RESV, LB1, LB2, LB3, CMP, SUS },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* === Triple status registers === */
+/* === GigaDevice === */
+/* GD25LQ05B, GD25LQ10B, GD25LQ20B */
+struct status_register gd25lq05_10_20b_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { SRP1, QE, SUS2, LB1, LB2, LB3, CMP, SUS1 },
+ { RESV, RESV, RESV, RESV, HPF, RESV, RESV, RESV },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* GD25Q32C, GD25Q64C */
+struct status_register gd25q32_64c_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { SRP1, QE, SUS2, LB1, LB2, LB3, CMP, SUS1 },
+ { RESV, RESV, RESV, RESV, HPF, DRV0, DRV1, RESV },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* GD25Q127C */
+struct status_register gd25q127c_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { SRP1, QE, SUS2, LB1, LB2, LB3, CMP, SUS1 },
+ { RESV, RESV, WPS, RESV, RESV, DRV0, DRV1, RST },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* GD25Q128C */
+struct status_register gd25q128c_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, BP3, BP4, SRP0 },
+ { SRP1, QE, SUS2, LB1, LB2, LB3, CMP, SUS1 },
+ { RESV, RESV, WPS, RESV, RESV, DRV0, DRV1, RST },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
+
+/* === Winbond === */
+/* W25Q128FW */
+struct status_register w25q128fw_sr = {
+ .layout = {
+ { WIP, WEL, BP0, BP1, BP2, TB, SEC, SRP0 },
+ { SRP1, QE, RESV, LB1, LB2, LB3, CMP, SUS },
+ { RESV, RESV, WPS, RESV, RESV, DRV0, DRV1, RST },
+ },
+ .read = &spi_read_status_register_generic,
+ .write = &spi_write_status_register_generic,
+ .print = &spi_prettyprint_status_register_generic,
+ .print_wp_mode = &spi_prettyprint_status_register_wp_generic,
+ .get_wp_mode = &get_wp_mode_generic,
+ .set_wp_mode = &set_wp_mode_generic,
+};
--
2.7.4
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