[flashrom] [PATCH] Drop non-existing support for nicnatsemi.

Stefan Tauner stefan.tauner at alumni.tuwien.ac.at
Sat Feb 27 17:07:08 CET 2016


This was meant to support National Semiconductor DP838* network cards
but was never tested successfully. The hardware does not seem to be
available on the market anymore and there was no development for
five years.

Signed-off-by: Stefan Tauner <stefan.tauner at alumni.tuwien.ac.at>
---
 Makefile        |  24 ------------
 flashrom.8.tmpl |   9 ++---
 flashrom.c      |  12 ------
 nicnatsemi.c    | 115 --------------------------------------------------------
 programmer.h    |   9 -----
 5 files changed, 3 insertions(+), 166 deletions(-)
 delete mode 100644 nicnatsemi.c

diff --git a/Makefile b/Makefile
index 1511eef..7b7d666 100644
--- a/Makefile
+++ b/Makefile
@@ -249,11 +249,6 @@ UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes
 else
 override CONFIG_NICREALTEK = no
 endif
-ifeq ($(CONFIG_NICNATSEMI), yes)
-UNSUPPORTED_FEATURES += CONFIG_NICNATSEMI=yes
-else
-override CONFIG_NICNATSEMI = no
-endif
 ifeq ($(CONFIG_NICINTEL), yes)
 UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes
 else
@@ -387,11 +382,6 @@ UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes
 else
 override CONFIG_NICREALTEK = no
 endif
-ifeq ($(CONFIG_NICNATSEMI), yes)
-UNSUPPORTED_FEATURES += CONFIG_NICNATSEMI=yes
-else
-override CONFIG_NICNATSEMI = no
-endif
 ifeq ($(CONFIG_RAYER_SPI), yes)
 UNSUPPORTED_FEATURES += CONFIG_RAYER_SPI=yes
 else
@@ -478,11 +468,6 @@ UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes
 else
 override CONFIG_NICREALTEK = no
 endif
-ifeq ($(CONFIG_NICNATSEMI), yes)
-UNSUPPORTED_FEATURES += CONFIG_NICNATSEMI=yes
-else
-override CONFIG_NICNATSEMI = no
-endif
 ifeq ($(CONFIG_NICINTEL), yes)
 UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes
 else
@@ -606,9 +591,6 @@ CONFIG_DRKAISER ?= yes
 # Always enable Realtek NICs for now.
 CONFIG_NICREALTEK ?= yes
 
-# Disable National Semiconductor NICs until support is complete and tested.
-CONFIG_NICNATSEMI ?= no
-
 # Always enable Intel NICs for now.
 CONFIG_NICINTEL ?= yes
 
@@ -860,12 +842,6 @@ PROGRAMMER_OBJS += nicrealtek.o
 NEED_LIBPCI += CONFIG_NICREALTEK
 endif
 
-ifeq ($(CONFIG_NICNATSEMI), yes)
-FEATURE_CFLAGS += -D'CONFIG_NICNATSEMI=1'
-PROGRAMMER_OBJS += nicnatsemi.o
-NEED_LIBPCI += CONFIG_NICNATSEMI
-endif
-
 ifeq ($(CONFIG_NICINTEL), yes)
 FEATURE_CFLAGS += -D'CONFIG_NICINTEL=1'
 PROGRAMMER_OBJS += nicintel.o
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index 9d8fcc3..2c68351 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -216,9 +216,6 @@ involving any chip access (probe/read/write/...). Currently supported are:
 .sp
 .BR "* nicrealtek" " (for flash ROMs on Realtek and SMC 1211 network cards)"
 .sp
-.BR "* nicnatsemi" " (for flash ROMs on National Semiconductor DP838* network \
-cards)"
-.sp
 .BR "* nicintel" " (for parallel flash ROMs on Intel 10/100Mbit network cards)
 .sp
 .BR "* gfxnvidia" " (for flash ROMs on NVIDIA graphics cards)"
@@ -638,7 +635,7 @@ syntax where
 .B content
 is an 8-bit hexadecimal value.
 .SS
-.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\
+.BR "nic3com" , " nicrealtek" , " nicintel", " nicintel_eeprom"\
 , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\
 , " satamv" , " atahpt", " atavia ", " atapromise " and " it8212 " programmers
 .IP
@@ -1057,7 +1054,7 @@ access (x86) and MSR access (x86).
 .B atavia
 needs PCI configuration space access.
 .sp
-.BR nic3com ", " nicrealtek " and " nicnatsemi "
+.BR nic3com " and " nicnatsemi "
 need PCI configuration space read access and raw I/O port access.
 .sp
 .B atahpt
@@ -1091,7 +1088,7 @@ need access to the respective USB device via libusb API version 1.0.
 .B dummy
 needs no access permissions at all.
 .sp
-.BR internal ", " nic3com ", " nicrealtek ", " nicnatsemi ", "
+.BR internal ", " nic3com ", " nicrealtek ", "
 .BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " atahpt ", " atavia " and " atapromise
 have to be run as superuser/root, and need additional raw access permission.
 .sp
diff --git a/flashrom.c b/flashrom.c
index 25e53f2..92e7abc 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -110,18 +110,6 @@ const struct programmer_entry programmer_table[] = {
 	},
 #endif
 
-#if CONFIG_NICNATSEMI == 1
-	{
-		.name			= "nicnatsemi",
-		.type			= PCI,
-		.devs.dev		= nics_natsemi,
-		.init			= nicnatsemi_init,
-		.map_flash_region	= fallback_map,
-		.unmap_flash_region	= fallback_unmap,
-		.delay			= internal_delay,
-	},
-#endif
-
 #if CONFIG_GFXNVIDIA == 1
 	{
 		.name			= "gfxnvidia",
diff --git a/nicnatsemi.c b/nicnatsemi.c
deleted file mode 100644
index ce22c94..0000000
--- a/nicnatsemi.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is part of the flashrom project.
- *
- * Copyright (C) 2010 Andrew Morgan <ziltro at ziltro.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#if defined(__i386__) || defined(__x86_64__)
-
-#include <stdlib.h>
-#include "flash.h"
-#include "programmer.h"
-#include "hwaccess.h"
-
-#define PCI_VENDOR_ID_NATSEMI	0x100b
-
-#define BOOT_ROM_ADDR		0x50
-#define BOOT_ROM_DATA		0x54
-
-static uint32_t io_base_addr = 0;
-const struct dev_entry nics_natsemi[] = {
-	{0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"},
-	{0x100b, 0x0022, NT, "National Semiconductor", "DP83820"},
-
-	{0},
-};
-
-static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
-				   chipaddr addr);
-static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
-				     const chipaddr addr);
-static const struct par_master par_master_nicnatsemi = {
-		.chip_readb		= nicnatsemi_chip_readb,
-		.chip_readw		= fallback_chip_readw,
-		.chip_readl		= fallback_chip_readl,
-		.chip_readn		= fallback_chip_readn,
-		.chip_writeb		= nicnatsemi_chip_writeb,
-		.chip_writew		= fallback_chip_writew,
-		.chip_writel		= fallback_chip_writel,
-		.chip_writen		= fallback_chip_writen,
-};
-
-int nicnatsemi_init(void)
-{
-	struct pci_dev *dev = NULL;
-
-	if (rget_io_perms())
-		return 1;
-
-	dev = pcidev_init(nics_natsemi, PCI_BASE_ADDRESS_0);
-	if (!dev)
-		return 1;
-
-	io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);
-	if (!io_base_addr)
-		return 1;
-
-	/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
-	 * in another. My NIC has MA16 connected to A16 on the boot ROM socket
-	 * so I'm assuming it is accessible. If not then next line wants to be
-	 * max_rom_decode.parallel = 65536; and the mask in the read/write
-	 * functions below wants to be 0x0000FFFF.
-	 */
-	max_rom_decode.parallel = 131072;
-	register_par_master(&par_master_nicnatsemi, BUS_PARALLEL);
-
-	return 0;
-}
-
-static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
-				   chipaddr addr)
-{
-	OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);
-	/*
-	 * The datasheet requires 32 bit accesses to this register, but it seems
-	 * that requirement might only apply if the register is memory mapped.
-	 * Bits 8-31 of this register are apparently don't care, and if this
-	 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
-	 * register seem to work fine. Due to that, we ignore the advice in the
-	 * data sheet.
-	 */
-	OUTB(val, io_base_addr + BOOT_ROM_DATA);
-}
-
-static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
-				     const chipaddr addr)
-{
-	OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
-	/*
-	 * The datasheet requires 32 bit accesses to this register, but it seems
-	 * that requirement might only apply if the register is memory mapped.
-	 * Bits 8-31 of this register are apparently don't care, and if this
-	 * register is I/O port mapped, 8 bit accesses to the lowest byte of the
-	 * register seem to work fine. Due to that, we ignore the advice in the
-	 * data sheet.
-	 */
-	return INB(io_base_addr + BOOT_ROM_DATA);
-}
-
-#else
-#error PCI port I/O access is not supported on this architecture yet.
-#endif
diff --git a/programmer.h b/programmer.h
index bd8e98d..c031ff7 100644
--- a/programmer.h
+++ b/programmer.h
@@ -39,9 +39,6 @@ enum programmer {
 #if CONFIG_NICREALTEK == 1
 	PROGRAMMER_NICREALTEK,
 #endif
-#if CONFIG_NICNATSEMI == 1
-	PROGRAMMER_NICNATSEMI,
-#endif
 #if CONFIG_GFXNVIDIA == 1
 	PROGRAMMER_GFXNVIDIA,
 #endif
@@ -411,12 +408,6 @@ int nicrealtek_init(void);
 extern const struct dev_entry nics_realtek[];
 #endif
 
-/* nicnatsemi.c */
-#if CONFIG_NICNATSEMI == 1
-int nicnatsemi_init(void);
-extern const struct dev_entry nics_natsemi[];
-#endif
-
 /* nicintel.c */
 #if CONFIG_NICINTEL == 1
 int nicintel_init(void);
-- 
Kind regards, Stefan Tauner





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