[flashrom] performance of flashrom (with FT2232H)

Boris Baykov dev at borisbaykov.com
Fri Jan 16 13:17:26 CET 2015

> I moved this discussion under another more appropriate subject
> as it is no more related to the original "Support for 4-bytes addressing".

>> > > Flashrom is slow because read and erase operations are written very
>> > > slow now. They could be easily changed to become faster in times or
>> > > in 10s of times. Probably I'll do this later. This should be another patch.
>> >
>> > I'll try to describe where these issues are...
>> >
>> > The read issue is in spi_read_chunked. There is a loop that reads data
>> > by pages (normally by 256 bytes). So, to read 32 MB flash we'll send
>> > 131k read commands with 3-7 ms wait for each.
>> Everything you say is true and optimizations you propose would be very
>> helpful, but the main question is - what introduces this 3-7ms delays. That is
>> NOT flashrom, nor it is libfti, nor libusb. The flash chips also don't seem to
>> require millisecond delays for READ/READ4B commands.

> I guess I know the reason and you are right in blaming 256-byte reads.
> The delay is introduced by USB itself as transactions happen in time slots.
> It is indeed needed to make flashrom fill the USB transaction buffer as much as possible
> before executing the transaction. FT2232H supports in MPSSE mode up to 64K of commands/data.

I did some quick tests by patching flashrom's code and it's really working.
I changed read chunk size from 256b to 64k and commented small erasers.

The main improvement is with read because the number of 3-7 ms delays are
decreased now in 256 times! Here one important thing exists - to read with
any chunk more than 256 bytes I have to set 5 MHz FTDI freq by settings
divisor=12 in programmer params. Even on 6 MHz with divisor=10 the read
is not working correctly. It seems to me that it may be changed by change
priority of the thread to realtime. Anyway on my Core-i7 3.2 in Linux
virtual machine with 2 cores given to VM and without any priority hacks
it's working maximum on 5 MHz.

Then I've got the following results for my w25q256fv chip with 5 MHz:

read    -       1 min                                   was 10 min
erase   -       ~3 min  [3.20 (by 64k), 2.40 (full)]    was about 15 min
write + verify  25 min  (256 bytes write chunk)         was about 1 hour

This flash chip can by written by 256b chunks only so the write is so long,
well some chips have 4k or even 64k pages. Such chips could be written in
less then 10 minutes.

Boris Baykov

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