[flashrom] [PATCH 2/2] Utilize new tested states for chipsets as well.
Stefan Tauner
stefan.tauner at alumni.tuwien.ac.at
Fri May 30 05:15:45 CEST 2014
Mark all ME-enabled Intel chipsets as DEP, alter print.c accordingly
(print_wiki.c was already prepared).
Signed-off-by: Stefan Tauner <stefan.tauner at alumni.tuwien.ac.at>
---
chipset_enable.c | 76 ++++++++++++++++++++++++++++----------------------------
print.c | 6 ++---
2 files changed, 41 insertions(+), 41 deletions(-)
diff --git a/chipset_enable.c b/chipset_enable.c
index 8be6dea..c62f877 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1479,38 +1479,38 @@ const struct penable chipset_enables[] = {
{0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0},
{0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
{0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
- {0x8086, 0x1c44, OK, "Intel", "Z68", enable_flash_pch6},
- {0x8086, 0x1c46, OK, "Intel", "P67", enable_flash_pch6},
+ {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6},
+ {0x8086, 0x1c46, DEP, "Intel", "P67", enable_flash_pch6},
{0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6},
{0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6},
- {0x8086, 0x1c4a, OK, "Intel", "H67", enable_flash_pch6},
+ {0x8086, 0x1c4a, DEP, "Intel", "H67", enable_flash_pch6},
{0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6},
{0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6},
{0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6},
{0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6},
- {0x8086, 0x1c4f, OK, "Intel", "QM67", enable_flash_pch6},
+ {0x8086, 0x1c4f, DEP, "Intel", "QM67", enable_flash_pch6},
{0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6},
{0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6},
- {0x8086, 0x1c54, OK, "Intel", "C204", enable_flash_pch6},
+ {0x8086, 0x1c54, DEP, "Intel", "C204", enable_flash_pch6},
{0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6},
- {0x8086, 0x1c5c, OK, "Intel", "H61", enable_flash_pch6},
- {0x8086, 0x1d40, OK, "Intel", "C60x/X79", enable_flash_pch6},
- {0x8086, 0x1d41, OK, "Intel", "C60x/X79", enable_flash_pch6},
- {0x8086, 0x1e44, OK, "Intel", "Z77", enable_flash_pch7},
+ {0x8086, 0x1c5c, DEP, "Intel", "H61", enable_flash_pch6},
+ {0x8086, 0x1d40, DEP, "Intel", "C60x/X79", enable_flash_pch6},
+ {0x8086, 0x1d41, DEP, "Intel", "C60x/X79", enable_flash_pch6},
+ {0x8086, 0x1e44, DEP, "Intel", "Z77", enable_flash_pch7},
{0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7},
{0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7},
{0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7},
- {0x8086, 0x1e49, OK, "Intel", "B75", enable_flash_pch7},
- {0x8086, 0x1e4a, OK, "Intel", "H77", enable_flash_pch7},
+ {0x8086, 0x1e49, DEP, "Intel", "B75", enable_flash_pch7},
+ {0x8086, 0x1e4a, DEP, "Intel", "H77", enable_flash_pch7},
{0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7},
- {0x8086, 0x1e55, OK, "Intel", "QM77", enable_flash_pch7},
+ {0x8086, 0x1e55, DEP, "Intel", "QM77", enable_flash_pch7},
{0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7},
- {0x8086, 0x1e57, OK, "Intel", "HM77", enable_flash_pch7},
+ {0x8086, 0x1e57, DEP, "Intel", "HM77", enable_flash_pch7},
{0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7},
{0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7},
{0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7},
{0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7},
- {0x8086, 0x1e5f, OK, "Intel", "NM70", enable_flash_pch7},
+ {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7},
{0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7},
{0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7},
{0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0},
@@ -1533,39 +1533,39 @@ const struct penable chipset_enables[] = {
{0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
{0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
{0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
- {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
- {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
- {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
- {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
- {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
- {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
- {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
- {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
- {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
- {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
- {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
- {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
+ {0x8086, 0x2810, DEP, "Intel", "ICH8/ICH8R", enable_flash_ich8},
+ {0x8086, 0x2811, DEP, "Intel", "ICH8M-E", enable_flash_ich8},
+ {0x8086, 0x2812, DEP, "Intel", "ICH8DH", enable_flash_ich8},
+ {0x8086, 0x2814, DEP, "Intel", "ICH8DO", enable_flash_ich8},
+ {0x8086, 0x2815, DEP, "Intel", "ICH8M", enable_flash_ich8},
+ {0x8086, 0x2910, DEP, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
+ {0x8086, 0x2912, DEP, "Intel", "ICH9DH", enable_flash_ich9},
+ {0x8086, 0x2914, DEP, "Intel", "ICH9DO", enable_flash_ich9},
+ {0x8086, 0x2916, DEP, "Intel", "ICH9R", enable_flash_ich9},
+ {0x8086, 0x2917, DEP, "Intel", "ICH9M-E", enable_flash_ich9},
+ {0x8086, 0x2918, DEP, "Intel", "ICH9", enable_flash_ich9},
+ {0x8086, 0x2919, DEP, "Intel", "ICH9M", enable_flash_ich9},
{0x8086, 0x3a10, NT, "Intel", "ICH10R Engineering Sample", enable_flash_ich10},
- {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
- {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
- {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
- {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
+ {0x8086, 0x3a14, DEP, "Intel", "ICH10DO", enable_flash_ich10},
+ {0x8086, 0x3a16, DEP, "Intel", "ICH10R", enable_flash_ich10},
+ {0x8086, 0x3a18, DEP, "Intel", "ICH10", enable_flash_ich10},
+ {0x8086, 0x3a1a, DEP, "Intel", "ICH10D", enable_flash_ich10},
{0x8086, 0x3a1e, NT, "Intel", "ICH10 Engineering Sample", enable_flash_ich10},
{0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5},
{0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5},
{0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5},
{0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5},
- {0x8086, 0x3b06, OK, "Intel", "H55", enable_flash_pch5},
- {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5},
+ {0x8086, 0x3b06, DEP, "Intel", "H55", enable_flash_pch5},
+ {0x8086, 0x3b07, DEP, "Intel", "QM57", enable_flash_pch5},
{0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5},
{0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5},
{0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5},
{0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5},
{0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5},
{0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5},
- {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_pch5},
+ {0x8086, 0x3b0f, DEP, "Intel", "QS57", enable_flash_pch5},
{0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5},
- {0x8086, 0x3b14, OK, "Intel", "3420", enable_flash_pch5},
+ {0x8086, 0x3b14, DEP, "Intel", "3420", enable_flash_pch5},
{0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5},
{0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5},
{0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
@@ -1578,19 +1578,19 @@ const struct penable chipset_enables[] = {
{0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Engineering Sample", enable_flash_pch8},
{0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Engineering Sample", enable_flash_pch8},
{0x8086, 0x8c43, NT, "Intel", "Lynx Point", enable_flash_pch8},
- {0x8086, 0x8c44, OK, "Intel", "Z87", enable_flash_pch8},
+ {0x8086, 0x8c44, DEP, "Intel", "Z87", enable_flash_pch8},
{0x8086, 0x8c45, NT, "Intel", "Lynx Point", enable_flash_pch8},
{0x8086, 0x8c46, NT, "Intel", "Z85", enable_flash_pch8},
{0x8086, 0x8c47, NT, "Intel", "Lynx Point", enable_flash_pch8},
{0x8086, 0x8c48, NT, "Intel", "Lynx Point", enable_flash_pch8},
{0x8086, 0x8c49, NT, "Intel", "HM86", enable_flash_pch8},
- {0x8086, 0x8c4a, OK, "Intel", "H87", enable_flash_pch8},
- {0x8086, 0x8c4b, OK, "Intel", "HM87", enable_flash_pch8},
+ {0x8086, 0x8c4a, DEP, "Intel", "H87", enable_flash_pch8},
+ {0x8086, 0x8c4b, DEP, "Intel", "HM87", enable_flash_pch8},
{0x8086, 0x8c4c, NT, "Intel", "Q85", enable_flash_pch8},
{0x8086, 0x8c4d, NT, "Intel", "Lynx Point", enable_flash_pch8},
{0x8086, 0x8c4e, NT, "Intel", "Q87", enable_flash_pch8},
{0x8086, 0x8c4f, NT, "Intel", "QM87", enable_flash_pch8},
- {0x8086, 0x8c50, OK, "Intel", "B85", enable_flash_pch8},
+ {0x8086, 0x8c50, DEP, "Intel", "B85", enable_flash_pch8},
{0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8},
{0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8},
{0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8},
diff --git a/print.c b/print.c
index 7bb788e..b63e8f7 100644
--- a/print.c
+++ b/print.c
@@ -395,7 +395,7 @@ static void print_supported_chipsets(void)
for (i = strlen("Chipset"); i < maxchipsetlen; i++)
msg_ginfo(" ");
- msg_ginfo("PCI IDs State\n\n");
+ msg_ginfo("PCI IDs Status\n\n");
for (c = chipset_enables; c->vendor_name != NULL; c++) {
msg_ginfo("%s", c->vendor_name);
@@ -404,8 +404,8 @@ static void print_supported_chipsets(void)
msg_ginfo("%s", c->device_name);
for (i = 0; i < maxchipsetlen - strlen(c->device_name); i++)
msg_ginfo(" ");
- msg_ginfo("%04x:%04x%s\n", c->vendor_id, c->device_id,
- (c->status == NT) ? " (untested)" : "");
+ msg_ginfo("%04x:%04x %s\n", c->vendor_id, c->device_id,
+ test_state_to_text(c->status));
}
}
--
Kind regards, Stefan Tauner
More information about the flashrom
mailing list