[flashrom] [commit] r1795 - trunk

[repository service]

Author: stefanct
Date: Fri May 16 23:39:48 2014
New Revision: 1795
URL: http://flashrom.org/trac/flashrom/changeset/1795

Log:
sbxxx: Add spispeed parameter.

Allow to set the SPI clock frequency on AMD chipsets with a programmer
parameter. If the parameter is given (and matches a possible value), the
SPI clock is set temporarily. Both registers are restored on programmer
shutdown.

Example: ./flashrom -p internal:spispeed="33 MHz" -V

Possible values for spispeed are "16.5 MHz", "22 MHz", "33 MHz", "66 MHz",
"100 MHZ" and "800 kHz" depending on the chipset generation.

Signed-off-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>

Modified:
   trunk/flashrom.8.tmpl
   trunk/sb600spi.c

Modified: trunk/flashrom.8.tmpl
==============================================================================
--- trunk/flashrom.8.tmpl	Fri May 16 23:39:33 2014	(r1794)
+++ trunk/flashrom.8.tmpl	Fri May 16 23:39:48 2014	(r1795)
@@ -357,6 +357,27 @@
 a layout file. This limitation might be removed in the future when we understand the details better and have
 received enough feedback from users. Please report the outcome if you had to use this option to write a chip.
 .sp
+An optional
+.B spispeed
+parameter specifies the frequency of the SPI bus where applicable (i.e.\& SB600 or later with an SPI flash chip
+directly attached to the chipset).
+Syntax is
+.sp
+.B "  flashrom \-p internal:spispeed=frequency"
+.sp
+where
+.B frequency
+can be
+.BR "'16.5\ MHz'" ", " "'22\ MHz'" ", " "'33\ MHz'" ", " "'66\ MHz'" ", " "'100\ MHZ'" ", or " "'800\ kHz'" "."
+Support of individual frequencies depends on the generation of the chipset:
+.sp
+* SB6xx, SB7xx, SP5xxx: from 16.5 MHz up to and including 33 MHz
+.sp
+* SB8xx, SB9xx, Hudson: from 16.5 MHz up to and including 66 MHz
+.sp
+* Yangtze (with SPI 100 engine as found in Kabini and Tamesh): all of them
+.sp
+The default is to use 16.5 MHz and disable Fast Reads.
 .TP
 .B Intel chipsets
 .sp

Modified: trunk/sb600spi.c
==============================================================================
--- trunk/sb600spi.c	Fri May 16 23:39:33 2014	(r1794)
+++ trunk/sb600spi.c	Fri May 16 23:39:48 2014	(r1795)
@@ -385,6 +385,29 @@
 	uint32_t tmp;
 	int8_t spispeed_idx = 3; /* Default to 16.5 MHz */
 
+	char *spispeed = extract_programmer_param("spispeed");
+	if (spispeed != NULL) {
+		if (strcasecmp(spispeed, "reserved") != 0) {
+			int i;
+			for (i = 0; i < ARRAY_SIZE(spispeeds); i++) {
+				if (strcasecmp(spispeeds[i].name, spispeed) == 0) {
+					spispeed_idx = i;
+					break;
+				}
+			}
+			/* Only Yangtze supports the second half of indices; no 66 MHz before SB8xx. */
+			if ((amd_gen < CHIPSET_YANGTZE && spispeed_idx > 3) ||
+			    (amd_gen < CHIPSET_SB89XX && spispeed_idx == 0))
+				spispeed_idx = -1;
+		}
+		if (spispeed_idx < 0) {
+			msg_perr("Error: Invalid spispeed value: '%s'.\n", spispeed);
+			free(spispeed);
+			return 1;
+		}
+		free(spispeed);
+	}
+
 	/* See the chipset support matrix for SPI Base_Addr below for an explanation of the symbols used.
 	 * bit   6xx   7xx/SP5100  8xx             9xx  hudson1  hudson234  yangtze
 	 * 18    rsvd  <-          fastReadEnable  ?    <-       ?          SpiReadMode[0]