[flashrom] [PATCH 0/5] check_trans and probe_spi_rdid_edi

[Antonio Ospite]

On Fri, 27 Jun 2014 18:00:03 +0200
Antonio Ospite <ao2 at ao2.it> wrote:

> On Wed,  3 Oct 2012 06:13:00 +0200
> Stefan Tauner <stefan.tauner at student.tuwien.ac.at> wrote:
> 
> > This patch set enables us to figure out if transactions will succeed
> > without executing them, which allows for a refactoring of
> > probe_spi_rdid_generic() which in consequence makes it possible to add
> > probe_spi_rdid_edi().
> >
> 
> Hi Stefan,
> 
> was there any development towards the functionality discussed
> in this old thread: check_trans() and probe_spi_rdid_edi()?
> 
> > The infrastructure code as a whole, but especially the ichspi code
> > is heavily modified. Please be aware of that if you test it on
> > mainboards.
> > 
> > Antonio: please rebase your Spansion patch on this one and extend it
> > to add actually two chips by using the full 32 bit model IDs
> > (0x20184d00, 0x20184d01) and .probe = probe_spi_rdid_edi.
> >
> 
> I am playing with these chips again.
> 
> FTR I am able to read and write S25FL129P1 chips using flashrom
> v0.9.7-r1782 which is in Debian ubstable, it supports the similar
> "S25FL128S......0", but only the bulk erase function worked
> (spi_block_erase_60), I wasn't able to do a block or sector erase; can
> this depend on the programmer (ft2232_spi)?
>

Ah, this may be because of the 64kB/256kB sector variants, I'll do more
test and post the results in the thread named:
"S25FL128S......0" onusbblaster_spi"

> I will send a proper log the next time I write a chip.
> 
> I have also tried to rebase this old set about check_trans() and
> probe_spi_rdid_edi() on top of the latest svn, I will check if the code
> still works but I wanted to ask first what the current status
> is, and if there is still interest to support rdid EDI.
>

The patch set rebased on top of flashrom v0.9.7-r1822 still works, at least with
ft2232_spi:

...
Probing for Spansion S25FL128S......0, 16384 kB: probe_spi_rdid_generic: id1 0x01, id2 0x2018
Found Spansion flash chip "S25FL128S......0" (16384 kB, SPI) on ft2232_spi.
Chip status register is 0x00.
Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set
Chip status register: Program Fail Flag (P_FAIL) is not set
Chip status register: Erase Fail Flag (E_FAIL) is not set
Chip status register: Block Protect 2 (BP2) is not set
Chip status register: Block Protect 1 (BP1) is not set
Chip status register: Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
Probing for Spansion S25FL129P......0, 16384 kB: probe_spi_rdid_generic: id1 0x01, id2 0x20184d01
Probing for Spansion S25FL129P......1, 16384 kB: probe_spi_rdid_generic: id1 0x01, id2 0x20184d01
Found Spansion flash chip "S25FL129P......1" (16384 kB, SPI) on ft2232_spi.
Chip status register is 0x00.
Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set
Chip status register: Bit 6 is not set
Chip status register: Bit 5 is not set
Chip status register: Block Protect 2 (BP2) is not set
Chip status register: Block Protect 1 (BP1) is not set
Chip status register: Block Protect 0 (BP0) is not set
Chip status register: Write Enable Latch (WEL) is not set
Chip status register: Write In Progress (WIP/BUSY) is not set
...


I see that besides EDI, some chips (S25FL128S and S25FL256S) support
also a 5 bytes id named ID-CFI (see section 11.2 Device ID and Common
Flash Interface (ID-CFI) Address Map in
http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf), so
these patches can allow to support that and differentiate even
between S25FL128S and S25FL129P which have the same EDI.

Thanks,
   Antonio

-- 
Antonio Ospite
http://ao2.it

A: Because it messes up the order in which people normally read text.
   See http://en.wikipedia.org/wiki/Posting_style
Q: Why is top-posting such a bad thing?