[flashrom] [PATCH 1/3] Refine Flash Component descriptor handling.

[Stefan Tauner]

On Tue, 12 Aug 2014 17:01:42 -0600
Marc Jones <marcj303 at gmail.com> wrote:

> I tested this branch on CC2: https://github.com/stefanct/flashrom/tree/intel
> 
> See attached logs.
> 
> 
> Flashrom views both chips as a single flash space. 

Yes, because the Intel chipsets do not allow the chip select pin to be
controlled by software directly. One has to use hardware sequencing and
there it does not make much sense to separate the two (although we know
the boundaries and could do so), or are there use cases for that in the
wild? Like using the first chip for everything but the BIOS region and
the second chip for the BIOS region only...?

> What is the correct
> method for only updating a single descriptor area?

There is only one descriptor (area), but I presume you are meaning a
region. Using a layout file allows to write only a part, but there are
patches that extend the usage to other actions as well.


The second (i.e. write) log is more or less useless due to:
"Warning: Chip content is identical to the requested image."
Although it would be somewhat interesting... because the descriptor
tells us that the flash chip has 256 B erase blocks, which is very
improbable. Do you know which flash chips are mounted there? (The first
one could be determined by forcing software sequencing via the
-p internal:ich_spi_mode=swseq). I'd also like to see a -VV log (you
could also use the -o <logfile> parameter ;) because with the flashrom
prints more detailed information about the descriptor... and I think
either the descriptor is wrong or they have changed something about the
erase block sizes too... I need to verify that before committing.
-- 
Kind regards/Mit freundlichen Grüßen, Stefan Tauner