[flashrom] [commit] r1747 - trunk
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Sun Sep 15 01:36:57 CEST 2013
Author: stefanct
Date: Sun Sep 15 01:36:57 2013
New Revision: 1747
URL: http://flashrom.org/trac/flashrom/changeset/1747
Log:
Use ich_generation parameter in enable functions prior to ICH7.
Follow the style used from ICH7 onwards to pass ich_generation
parameter to lower-level functions on older ICH chipsets too.
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>
Modified:
trunk/chipset_enable.c
trunk/programmer.h
Modified: trunk/chipset_enable.c
==============================================================================
--- trunk/chipset_enable.c Sun Sep 15 01:36:53 2013 (r1746)
+++ trunk/chipset_enable.c Sun Sep 15 01:36:57 2013 (r1747)
@@ -314,14 +314,12 @@
return 0;
}
-static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
+static int enable_flash_ich0(struct pci_dev *dev, const char *name)
{
- /*
- * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
- * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
- * FB_DEC_EN2.
- */
internal_buses_supported = BUS_FWH;
+ /* FIXME: Make this use enable_flash_ich_4e() too and add IDSEL support. Unlike later chipsets,
+ * ICH and ICH-0 do only support mapping of the top-most 4MB and therefore do only feature
+ * FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
return enable_flash_ich(dev, name, 0x4e);
}
@@ -441,7 +439,38 @@
return 0;
}
-static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
+static int enable_flash_ich_4e(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation)
+{
+ /*
+ * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
+ * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
+ * FB_DEC_EN2.
+ */
+ internal_buses_supported = BUS_FWH;
+ return enable_flash_ich(dev, name, 0x4e);
+}
+
+static int enable_flash_ich2(struct pci_dev *dev, const char *name)
+{
+ return enable_flash_ich_4e(dev, name, CHIPSET_ICH2);
+}
+
+static int enable_flash_ich3(struct pci_dev *dev, const char *name)
+{
+ return enable_flash_ich_4e(dev, name, CHIPSET_ICH3);
+}
+
+static int enable_flash_ich4(struct pci_dev *dev, const char *name)
+{
+ return enable_flash_ich_4e(dev, name, CHIPSET_ICH4);
+}
+
+static int enable_flash_ich5(struct pci_dev *dev, const char *name)
+{
+ return enable_flash_ich_4e(dev, name, CHIPSET_ICH5);
+}
+
+static int enable_flash_ich_dc(struct pci_dev *dev, const char *name, enum ich_chipset ich_generation)
{
int err;
@@ -456,6 +485,11 @@
return enable_flash_ich(dev, name, 0xdc);
}
+static int enable_flash_ich6(struct pci_dev *dev, const char *name)
+{
+ return enable_flash_ich_dc(dev, name, CHIPSET_ICH6);
+}
+
static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
{
uint16_t old, new;
@@ -575,7 +609,7 @@
}
/* Enable Flash Writes */
- ret = enable_flash_ich_dc(dev, name);
+ ret = enable_flash_ich_dc(dev, name, ich_generation);
if (ret == ERROR_FATAL)
return ret;
@@ -1495,21 +1529,21 @@
{0x8086, 0x1e5f, NT, "Intel", "NM70", enable_flash_pch7},
{0x8086, 0x2310, NT, "Intel", "DH89xxCC", enable_flash_pch7},
{0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7},
- {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
- {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
- {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
- {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
- {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich_4e},
- {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
- {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
- {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
- {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
- {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
- {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
- {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
- {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
- {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich_dc},
- {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
+ {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0},
+ {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0},
+ {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2},
+ {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2},
+ {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2},
+ {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich3},
+ {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich3},
+ {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich4},
+ {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich4},
+ {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich5},
+ {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich5},
+ {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6},
+ {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6},
+ {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6},
+ {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6},
{0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
{0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
{0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
Modified: trunk/programmer.h
==============================================================================
--- trunk/programmer.h Sun Sep 15 01:36:53 2013 (r1746)
+++ trunk/programmer.h Sun Sep 15 01:36:57 2013 (r1747)
@@ -554,10 +554,15 @@
int default_spi_write_aai(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
int register_spi_programmer(const struct spi_programmer *programmer);
-/* The following enum is needed by ich_descriptor_tool and ich* code. */
+/* The following enum is needed by ich_descriptor_tool and ich* code as well as in chipset_enable.c. */
enum ich_chipset {
CHIPSET_ICH_UNKNOWN,
- CHIPSET_ICH7 = 7,
+ CHIPSET_ICH2 = 2,
+ CHIPSET_ICH3,
+ CHIPSET_ICH4,
+ CHIPSET_ICH5,
+ CHIPSET_ICH6,
+ CHIPSET_ICH7,
CHIPSET_ICH8,
CHIPSET_ICH9,
CHIPSET_ICH10,
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