[flashrom] Added chipsets

Николай Николаев evrinoma at gmail.com
Tue May 28 07:59:54 CEST 2013

---------- Forwarded message ----------
From: Николай Николаев <evrinoma at gmail.com>
Date: 2013/5/28
Subject: Re: [flashrom] Added chipsets
To: Steven Zakulec <spzakulec at gmail.com>

Hi Steven,

Other people can provide more details on the general case, but in this
> instance, with only a WREN instruction, the FEATURE line should be:
 I've been informed by others that your original idea of dropping the
> FEATURE line is actually correct, so you should do that instead of what I
> proposed.
i dropped this line because this line for chips fetch

 Numonyx N25Q00AA13-
>>> I'll admit I don't really know how this chip works, but it seems there
>>> should be a 3rd eraseblock from the description of the memory organization
>>> (datasheet is Rev E, 2/12):
>>> Memory Configuration and Block Diagram
>>> The memory is a stacked device comprised of four 256Mb chips. Each chip
>>> is internally
>>> partitioned into two 128Mb segments. Each page of memory can be
>>> individually pro-
>>> grammed. Bits are programmed from one through zero. The device is
>>> subsector, sector,
>>> or single 256Mb chip erasable, but not page-erasable. Bits are erased
>>> from zero through
>>> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048
>>> sectors (64KB
>>> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each);
>>> and 64 OTP
>>> bytes are located outside the main memory array.
>>> You've got:
>>> +                .eraseblocks = { {4 * 1024, 32768 } },
>>> +               .block_erase = spi_block_erase_20,
>>> +            }, {
>>> +                .eraseblocks = { {64 * 1024, 2048 } },
>>> +               .block_erase = spi_block_erase_d8,
>>> There's a die erase opcode, which I am unfamiliar with- maybe it handles
>>> erasing a single 256Mb chip at a time?
>> You right this chip used a four 256 Mb chips. And 256 Mb chip has a three
>> instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands.
>> But chip N25Q00AA13 has a other op-code to initiate die erase command
>> C4 (hex)
>> So, how do you do a single-chip erase for this chip?
I think this function is feature, because use "not general" op-code C4 for
die erase command. Also first we need to write a special function feature
extended addressing for chips more than 128 mb, after that we will think
about how to initiate die erase instruction.

What data sheets do you have for those chips?  The ones below list the
> small sector erase op-code as D7.
> LE25FW418A: 61709 SY 20090428-S00004 No.A1432
> LE25FW808: 61009 SY IM 20090319-S00003 No.A0839
> LE25FW806: 70208 SY IM 20070628-S00004 No.A0838
 I have a equivalence data sheets.
 LE25FW808 has a general op-code 20(hex) to initiate small sector erase.
Other chips use a feature op-code as D7.

With best regards Nikolay Nikolaev

With best regards Nikolay Nikolaev
С Уважением Николаев Николай
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