[flashrom] [coreboot] Enabling Dediprog by default in flashrom

Alexandre Pereira da Silva aletes.xgr at gmail.com
Tue Jul 2 05:12:28 CEST 2013

I think its safe to use a read opcode by default.

The DediProg can't reach high clock rates, well below the limit for the
normal read on most memories.

I have a DediProg available for testing.

Em 16/06/2013 11:10, "Stefan Tauner" <stefan.tauner at student.tuwien.ac.at>

> Hi,
> the release of flashrom 0.9.7 is imminent and I would really like to
> enable the Dediprog programmer by default. Carl-Daniel informed me that
> the only problem is that we do not know which opcode is actually used
> for reading on the SPI bus. It could be that we initiate a fast read
> (0x0b) instead of a normal read (0x03). This would work with the
> majority of flash chips but would not with others where flashrom
> should normally work. Since we are not sure we don't want to enable it
> without further consideration/testing/warning messages. Furthermore
> not all chips supporting fast read have this fact noted in their
> datashets. So testing any apparently non-fast read chip does not
> suffice. We would rather be able to check the opcode on the SPI bus
> with a logic analyzer directly. Are there any Dediprog users who can
> help us with that please?
> --
> Kind regards/Mit freundlichen Grüßen, Stefan Tauner
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.flashrom.org/pipermail/flashrom/attachments/20130702/2f31e6e2/attachment.html>

More information about the flashrom mailing list