[flashrom] [PATCH 1/5] rayer_spi: Improve support for different pinouts
Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006 at gmx.net
Sat Apr 6 03:12:22 CEST 2013
Here is the same patch, with my suggested changes and some other stuff
on top (constification, naming the Xilinx DLC-5 cable "dlc5" in
anticipation of the buffered DLC-5 variant) to avoid changing things
twice. I tried to dig up the history of this patch, hopefully I got it
right.
Am 01.04.2013 23:55 schrieb Kyösti Mälkki:
> Create a list of programmer types with names. This list could be
> listed with flashrom -L in follow-up patches.
>
> Handle a bit in status register that is inverted, this will be used
> in different future programmer types.
>
> Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
> Tested-by: Maksim Kuleshov <mmcx at mail.ru>
> Acked-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
rayer_spi: Rework handling of programmer types
Store rayer_spi programmer types with configuration data in an array.
Bit 7 of the LPT status register is inverted, automatically handle this
for future users.
The Xilinx DLC-5 cable is now selected with type=dlc-5 instead of
dev=xilinx.
Patch originally by Maksim Kuleshov, reworked by Kyösti Mälkki and
Carl-Daniel Hailfinger.
Maksim/Kyösti, can I get your signoff?
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Index: flashrom-maksim_rayer_spi_rework_type_selection/rayer_spi.c
===================================================================
--- flashrom-maksim_rayer_spi_rework_type_selection/rayer_spi.c (Revision 1667)
+++ flashrom-maksim_rayer_spi_rework_type_selection/rayer_spi.c (Arbeitskopie)
@@ -19,6 +19,7 @@
/* Driver for the SPIPGM hardware by "RayeR" Martin Rehak.
* See http://rayer.ic.cz/elektro/spipgm.htm for schematics and instructions.
+ * Other LPT-based SPI programming hardware is supported as well.
*/
/* This driver uses non-portable direct I/O port accesses which won't work on
@@ -37,22 +38,50 @@
#include "programmer.h"
#include "hwaccess.h"
-enum rayer_type {
- TYPE_RAYER,
- TYPE_XILINX_DLC5,
-};
-
/* We have two sets of pins, out and in. The numbers for both sets are
* independent and are bitshift values, not real pin numbers.
* Default settings are for the RayeR hardware.
*/
-/* Pins for master->slave direction */
-static int rayer_cs_bit = 5;
-static int rayer_sck_bit = 6;
-static int rayer_mosi_bit = 7;
-/* Pins for slave->master direction */
-static int rayer_miso_bit = 6;
+struct noid_dev_entry {
+ const char *type;
+ const enum test_state status;
+ const char *description;
+ const void *dev_data;
+};
+
+struct rayer_pinout {
+ uint8_t cs_bit;
+ uint8_t sck_bit;
+ uint8_t mosi_bit;
+ uint8_t miso_bit;
+ void (*init)(void *);
+ int (*shutdown)(void *);
+};
+
+static const struct rayer_pinout rayer_spipgm = {
+ .cs_bit = 5,
+ .sck_bit = 6,
+ .mosi_bit = 7,
+ .miso_bit = 6,
+};
+
+static const struct rayer_pinout xilinx_dlc5 = {
+ .cs_bit = 2,
+ .sck_bit = 1,
+ .mosi_bit = 0,
+ .miso_bit = 4,
+};
+
+/* List of supported devices, first one is the default. */
+static const struct noid_dev_entry rayer_spi_devs[] = {
+ {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm},
+ {"dlc-5", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5},
+ {0},
+};
+
+static struct rayer_pinout *pinout = NULL;
+
static uint16_t lpt_iobase;
/* Cached value of last byte sent. */
@@ -60,22 +89,22 @@
static void rayer_bitbang_set_cs(int val)
{
- lpt_outbyte &= ~(1 << rayer_cs_bit);
- lpt_outbyte |= (val << rayer_cs_bit);
+ lpt_outbyte &= ~(1 << pinout->cs_bit);
+ lpt_outbyte |= (val << pinout->cs_bit);
OUTB(lpt_outbyte, lpt_iobase);
}
static void rayer_bitbang_set_sck(int val)
{
- lpt_outbyte &= ~(1 << rayer_sck_bit);
- lpt_outbyte |= (val << rayer_sck_bit);
+ lpt_outbyte &= ~(1 << pinout->sck_bit);
+ lpt_outbyte |= (val << pinout->sck_bit);
OUTB(lpt_outbyte, lpt_iobase);
}
static void rayer_bitbang_set_mosi(int val)
{
- lpt_outbyte &= ~(1 << rayer_mosi_bit);
- lpt_outbyte |= (val << rayer_mosi_bit);
+ lpt_outbyte &= ~(1 << pinout->mosi_bit);
+ lpt_outbyte |= (val << pinout->mosi_bit);
OUTB(lpt_outbyte, lpt_iobase);
}
@@ -83,8 +112,8 @@
{
uint8_t tmp;
- tmp = INB(lpt_iobase + 1);
- tmp = (tmp >> rayer_miso_bit) & 0x1;
+ tmp = INB(lpt_iobase + 1) ^ 0x80; // bit 7 is inverted
+ tmp = (tmp >> pinout->miso_bit) & 0x1;
return tmp;
}
@@ -99,8 +128,9 @@
int rayer_spi_init(void)
{
+ /* Pick the first entry in rayer_spi_devs as default. */
+ const struct noid_dev_entry *dev = rayer_spi_devs;
char *arg = NULL;
- enum rayer_type rayer_type = TYPE_RAYER;
/* Non-default port requested? */
arg = extract_programmer_param("iobase");
@@ -138,36 +168,18 @@
arg = extract_programmer_param("type");
if (arg) {
- if (!strcasecmp(arg, "rayer")) {
- rayer_type = TYPE_RAYER;
- } else if (!strcasecmp(arg, "xilinx")) {
- rayer_type = TYPE_XILINX_DLC5;
- } else {
- msg_perr("Error: Invalid device type specified.\n");
+ for (; dev->type; ++dev)
+ if (!strcasecmp(arg, dev->type))
+ break;
+ if(!dev->type) {
+ msg_perr("Error: Invalid device type \"%s\"specified.\n", arg);
free(arg);
return 1;
}
+ free(arg);
}
- free(arg);
- switch (rayer_type) {
- case TYPE_RAYER:
- msg_pdbg("Using RayeR SPIPGM pinout.\n");
- /* Bits for master->slave direction */
- rayer_cs_bit = 5;
- rayer_sck_bit = 6;
- rayer_mosi_bit = 7;
- /* Bits for slave->master direction */
- rayer_miso_bit = 6;
- break;
- case TYPE_XILINX_DLC5:
- msg_pdbg("Using Xilinx Parallel Cable III (DLC 5) pinout.\n");
- /* Bits for master->slave direction */
- rayer_cs_bit = 2;
- rayer_sck_bit = 1;
- rayer_mosi_bit = 0;
- /* Bits for slave->master direction */
- rayer_miso_bit = 4;
- }
+ msg_pinfo("Using %s pinout.\n", dev->description);
+ pinout = (struct rayer_pinout *) dev->dev_data;
if (rget_io_perms())
return 1;
@@ -175,6 +187,11 @@
/* Get the initial value before writing to any line. */
lpt_outbyte = INB(lpt_iobase);
+ if (pinout->shutdown)
+ register_shutdown(pinout->shutdown, pinout);
+ if (pinout->init)
+ pinout->init(pinout);
+
if (bitbang_spi_init(&bitbang_spi_master_rayer))
return 1;
Index: flashrom-maksim_rayer_spi_rework_type_selection/flashrom.8
===================================================================
--- flashrom-maksim_rayer_spi_rework_type_selection/flashrom.8 (Revision 1667)
+++ flashrom-maksim_rayer_spi_rework_type_selection/flashrom.8 (Arbeitskopie)
@@ -715,7 +715,7 @@
syntax where
.B model
can be
-.BR rayer " for the RayeR cable or " xilinx " for the Xilinx Parallel Cable III
+.BR rayer " for the RayeR cable or " dlc-5 " for the Xilinx Parallel Cable III
(DLC 5).
.sp
More information about the RayeR hardware is available at
--
http://www.hailfinger.org/
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