[flashrom] MSI GF615M-P33: superiotool -dV

[Carl-Daniel Hailfinger]

Hi Kim,

Am 13.03.2012 09:39 schrieb Kim Johansson:
> Den Tuesday 13 March 2012 01.16.26 skrev Stefan Tauner:
>> On Sat, 10 Mar 2012 21:10:06 +0100
>>
>> Kim Johansson <kbkj at telia.com> wrote:
>>> flashrom v0.9.5.2-r1516 on Linux 2.6.35 (i686)
>>>
>>> Calibrating delay loop... OK. Initializing internal programmer
>>> DMI string system-manufacturer: "MICRO-STAR INTERNATIONAL CO.,LTD"
>>> DMI string system-product-name: "MS-7597"
>>> DMI string system-version: "1.0"
>>> DMI string baseboard-manufacturer: "MICRO-STAR INTERNATIONAL CO.,LTD"
>>> DMI string baseboard-product-name: "GF615M-P33  (MS-7597)"
>>> DMI string baseboard-version: "1.0"
>>> DMI string chassis-type: "Desktop"
>>> Found chipset "NVIDIA MCP61" with PCI ID 10de:03e0. Enabling flash
>>> write... This chipset is not really supported yet. Guesswork... ISA/LPC
>>> bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0
>>> Flash bus type is SPI

Not good. This bit usually is a very good indicator that the flash chip
is attached via chipset SPI, not via LPC (as would be the case with
flash translation in the Super I/O chip).


>>> SMBus device 10de:03eb at 00:01:1
>>> MCP SPI BAR is at 0xfec80000
>>> SPI control is 0x0012, req=0, gnt=0
>>> Please send the output of "flashrom -V" to flashrom at flashrom.org with
>>> your board name: flashrom -V as the subject to help us finish support for
>>> your chipset. Thanks.
>>> OK.
>>> The following protocols are supported: SPI.
>>> […]
>>> No EEPROM/flash device found.
>> your log looks suspicious, maybe you have found a bug in our MCP61 code
>> or the flash is not attached to the southbridge, but the fintek chip.
>> could you please send us the output of "superiotool -dV", thanks.
> superiotool
> [...]
> Probing for Fintek Super I/O at 0x4e...
> Found Fintek F71889 (vid=0x3419, id=0x2307) at 0x4e
> Register dump:
> idx 20 21 23 24 25 26 27 28  2a 2b 2c 2d
> val 07 23 19 34 00 80 50 00  c0 c0 00 08
> def 07 23 19 34 00 00 00 00  f0 30 00 08
> LDN 0x00 (Floppy)
> idx 30 60 61 70 74 f0 f2 f4
> val 01 03 f0 06 02 0e ff 00
> def 01 03 f0 06 02 0e 03 00
> LDN 0x01 (COM1)
> idx 30 60 61 70 f0
> val 01 03 f8 04 00
> def 01 03 f8 04 00
> LDN 0x02 (COM2)
> idx 30 60 61 70 f0 f1
> val 00 02 f8 03 00 44
> def 01 02 f8 03 00 04
> LDN 0x03 (Parallel port)
> idx 30 60 61 70 74 f0
> val 01 03 78 07 04 3c
> def 01 03 78 07 03 42
> LDN 0x04 (Hardware monitor)
> idx 30 60 61 70
> val 01 0a 00 00
> def 01 02 95 00
> LDN 0x05 (Keyboard)
> idx 30 60 61 70 72 fe
> val 01 00 60 01 0c 01
> def 01 00 60 01 0c 81
> LDN 0x06 (GPIO)
> idx 80 81 82 83 90 91 92 93  a0 a1 a2 a3 b0 b1 b2 c0  c1 c2 c3 d0 d1 d2 d3 e0  e1 e2 e3 f0 f1 f2 f3 fe  ff
> val 00 ff 00 00 00 ff ff 00  00 1f 1f 00 00 ff 00 00  ff ff 00 80 ff 9a 00 08  7f 68 00 40 7f 50 40 15  1c
> def 00 ff NA 00 00 ff NA 00  00 1f NA 00 00 ff NA 00  ff NA 00 00 ff NA 00 00  7f NA 00 00 7f NA 00 00  00
> LDN 0x07 (VID)
> idx 30 60 61
> val 00 0a e0
> def 00 00 00
> LDN 0x08 (SPI)
> idx f0 f1 f2 f3 f4 f5 f6 f7  f8 fa fb fc fd fe ff
> val 00 04 01 70 f8 00 00 08  00 00 00 00 00 00 00
> def 00 RR 01 00 00 00 00 00  00 00 00 00 00 00 00
> LDN 0x0a (PME, ACPI)
> idx 30 f0 f1 f4 f5 f6
> val 01 00 6b 06 1c 07
> def 00 00 00 26 1c 07
> LDN 0x0b (VREF)
> idx f0 f1 f2 f3 ff
> val 64 64 64 00 00
> def 64 64 64 00 00

NOLDN register 0x27 indicates that the Fintek Super I/O chip indeed has
SPI translation switched on.

Could you try this patch against latest flashrom and report the verbose
output of flashrom?
http://patchwork.coreboot.org/patch/3440/ (click on the "patch" link in
the line which starts with "Download").
Instead of downloading manually, you could also run the following
command in your flashrom source tree:
curl -s http://patchwork.coreboot.org/patch/3440/raw/|patch -p1

That patch will not magically add the needed feature to flashrom, but it
will show us what to expect and how to proceed.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/