[flashrom] Using flashrom with Intel Ibex Peak (PCH 3420) amd M25P64 flash works

[Stefan Tauner]

On Fri, 25 May 2012 15:56:17 -0400
"Gary Hannon" <ghannon at cspi.com> wrote:

> 
> Great tool.  I found this after lunch and had it working 
> and verified by 3:30.
> 
> Attached are the Verbose output dumps that you were 
> hoping to get on new arch's.
> 
> I was able to read, erase, program and verify the flash.
thanks! i have marked it as tested in my local repository and will
commit it later.

> We will soon have a board that uses 2 flashes, each 64Mb.
> I will also send feedback of what that looks like.
> 
> Can this tool specify which chip select to use when 
> writing, or do I need to create a map?   We will have the 
> descriptors in each flash calling the other flash as 
> the Platform Data region.  Our board has a way to steer 
> which chip gets CS0 and which gets CS1 for having a 
> failover incase a BIOS setting makes the board unbootable.

actually there is no way to directly interact with the chip select pins
with host software. also, you only need (and the hardware supports just)
one single descriptor that describes both devices and a full raid1-like
failover is not possible.
at least that's what i believe to have found out by studying various
datasheets and restricted intel manuals. you will probably need to
change your design (ideas).

apart from that, flashrom supports dual-chip based designs. this is
done by letting the hardware do most of the work in so-called hardware
sequencing mode. see the related documentation in the manpage for
details and there are also various bits scattered in the mailing list
archive. and there is my blog post about hardware sequencing from last
year:
http://blogs.coreboot.org/blog/2011/06/11/gsoc-2011-flashrom-part-1/
this may not be entirely correct, maybe not everything was understood
back then.

-- 
Kind regards/Mit freundlichen Grüßen, Stefan Tauner