[flashrom] [PATCH 4/5] Add spi_block_erase_62.

[Stefan Tauner]

This is used by the AT25F series (only?), but is generic enough to reside in spi25.c.
The only currently supported chip is the AT25F512B. Other members of that series
need some additional infrastructure code, hence this patch adds the erase function to
the AT25F512B only.

Signed-off-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>
---
 chipdrivers.h |    1 +
 flashchips.c  |    3 +++
 spi.h         |    5 +++++
 spi25.c       |   47 +++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 56 insertions(+), 0 deletions(-)

diff --git a/chipdrivers.h b/chipdrivers.h
index 420564d..44eca65 100644
--- a/chipdrivers.h
+++ b/chipdrivers.h
@@ -40,6 +40,7 @@ int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int b
 int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
 int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
 int spi_block_erase_60(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
+int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
 int spi_block_erase_c7(struct flashctx *flash, unsigned int addr, unsigned int blocklen);
 int spi_chip_write_1(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
 int spi_chip_write_256(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
diff --git a/flashchips.c b/flashchips.c
index 3656794..80f29f6 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -1679,6 +1679,9 @@ const struct flashchip flashchips[] = {
 			}, {
 				.eraseblocks = { {64 * 1024, 1} },
 				.block_erase = spi_block_erase_c7,
+			}, {
+				.eraseblocks = { {64 * 1024, 1} },
+				.block_erase = spi_block_erase_62,
 			}
 		},
 		.printlock	= spi_prettyprint_status_register_at25f512b,
diff --git a/spi.h b/spi.h
index b908603..adb9109 100644
--- a/spi.h
+++ b/spi.h
@@ -61,6 +61,11 @@
 #define JEDEC_CE_60_OUTSIZE	0x01
 #define JEDEC_CE_60_INSIZE	0x00
 
+/* Chip Erase 0x62 is supported by Atmel AT25F chips. */
+#define JEDEC_CE_62		0x62
+#define JEDEC_CE_62_OUTSIZE	0x01
+#define JEDEC_CE_62_INSIZE	0x00
+
 /* Chip Erase 0xc7 is supported by SST/ST/EON/Macronix chips. */
 #define JEDEC_CE_C7		0xc7
 #define JEDEC_CE_C7_OUTSIZE	0x01
diff --git a/spi25.c b/spi25.c
index 5c5048d..0d02559 100644
--- a/spi25.c
+++ b/spi25.c
@@ -488,6 +488,43 @@ int spi_chip_erase_60(struct flashctx *flash)
 	return 0;
 }
 
+int spi_chip_erase_62(struct flashctx *flash)
+{
+	int result;
+	struct spi_command cmds[] = {
+	{
+		.writecnt	= JEDEC_WREN_OUTSIZE,
+		.writearr	= (const unsigned char[]){ JEDEC_WREN },
+		.readcnt	= 0,
+		.readarr	= NULL,
+	}, {
+		.writecnt	= JEDEC_CE_62_OUTSIZE,
+		.writearr	= (const unsigned char[]){ JEDEC_CE_62 },
+		.readcnt	= 0,
+		.readarr	= NULL,
+	}, {
+		.writecnt	= 0,
+		.writearr	= NULL,
+		.readcnt	= 0,
+		.readarr	= NULL,
+	}};
+	
+	result = spi_send_multicommand(flash, cmds);
+	if (result) {
+		msg_cerr("%s failed during command execution\n",
+			__func__);
+		return result;
+	}
+	/* Wait until the Write-In-Progress bit is cleared.
+	 * This usually takes 2-5 s, so wait in 100 ms steps.
+	 */
+	/* FIXME: We assume spi_read_status_register will never fail. */
+	while (spi_read_status_register(flash) & JEDEC_RDSR_BIT_WIP)
+		programmer_delay(100 * 1000);
+	/* FIXME: Check the status register for errors. */
+	return 0;
+}
+
 int spi_chip_erase_c7(struct flashctx *flash)
 {
 	int result;
@@ -712,6 +749,16 @@ int spi_block_erase_60(struct flashctx *flash, unsigned int addr,
 	return spi_chip_erase_60(flash);
 }
 
+int spi_block_erase_62(struct flashctx *flash, unsigned int addr, unsigned int blocklen)
+{
+	if ((addr != 0) || (blocklen != flash->total_size * 1024)) {
+		msg_cerr("%s called with incorrect arguments\n",
+			__func__);
+		return -1;
+	}
+	return spi_chip_erase_62(flash);
+}
+
 int spi_block_erase_c7(struct flashctx *flash, unsigned int addr,
 		       unsigned int blocklen)
 {
-- 
1.7.1