[flashrom] SUCCESS: MX25L1605 on Thinkpad X60s [was: FAILED]

Peter Stuge peter at stuge.se
Tue Apr 24 18:56:14 CEST 2012


Motiejus Jakštys wrote:
> I carefully followed the instructions by Peter Stuge:
> http://comments.gmane.org/gmane.linux.bios/69354

> Erasing and writing flash chip... spi_block_erase_20 failed during command execution at address 0x0
> Reading current flash chip contents... done. spi_block_erase_52 failed during command execution at address 0x0

The above are OK. flashrom tries different erase commands and the
0x20 and 0x52 fail. (But then 0xd8 is tried and that succeeds.)

> Reading current flash chip contents... done. Transaction error!

I'm not sure why this Transaction error is printed, but it's not

> spi_block_erase_d8 failed during command execution at address 0x1f0000

This looks bad but it is actually an indication of success. This
means that your flash chip was erased and written by flashrom up
until the last 64kb, which always remains write protected with the
factory BIOS.

> Your flash chip is in an unknown state.

This is not really true. We know that your flash chip has been erased
and written with the first 2048-64=1984 kb of coreboot.rom.

> Where should I start fixing the problem? The computer is running.

If bucts shows this output:

# ./bucts
bucts utility version '2'
Using LPC bridge 8086:27b9 at 0000:1f.00
Current BUC.TS=1 - 64kb address ranges at 0xFFFE0000 and 0xFFFF0000 are swapped

..the important part being Current BUC.TS=1 on the last line, and
you've followed the steps carefully, then you should reboot now and
let your machine run coreboot for the first time! :)

There is one comment to make, the dd commands I wrote in that email
can not be copypasted into the shell, the sizeof() part in particular
requires manually inserting the size of the coreboot.rom file into
the command. If you didn't do this then please go back into the
coreboot directory, rm -rf build, and start over with the dd commands
on a freshly built coreboot.rom file.


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