[flashrom] [PATCH 09/11] add macros and pretty printing for "Host Lower Vendor Specific Component Capabilities" registers

[Stefan Tauner]

there are two of them: lower and upper.  they are only useful for hardware sequencing and indicate properties of the respective flash chip/address space. the VSCC registers describe the properties of the address space lower and equal or above than FPBA.

Signed-off-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>
---
 ichspi.c |   41 +++++++++++++++++++++++++++++++++++++++++
 1 files changed, 41 insertions(+), 0 deletions(-)

diff --git a/ichspi.c b/ichspi.c
index fd983ce..c8d8432 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -131,6 +131,25 @@
 #define ICH9_REG_BBAR		0xA0	/* 32 Bits BIOS Base Address Configuration */
 #define BBAR_MASK	0x00ffff00		/* 8-23: Bottom of System Flash */
 
+#define ICH9_REG_LVSCC		0xC4	/* 32 Bits Host Lower Vendor Specific Component Capabilities */
+#define ICH9_REG_UVSCC		0xC8	/* 32 Bits Host Upper Vendor Specific Component Capabilities */
+/* Field locations and semantics for LVSCC and UVSCC are equal therefore they
+ * share the same macros. */
+#define VSCC_EBS_OFF		0	/* 0-1: Block/Sector Erase Size */
+#define VSCC_EBS			(0x3 << VSCC_EBS_OFF)
+#define VSCC_WG_OFF		2	/* 2: Write Granularity */
+#define VSCC_WG				(0x1 << VSCC_WG_OFF)
+#define VSCC_WSR_OFF		3	/* 3: Write Status Required */
+#define VSCC_WSR			(0x1 << VSCC_WSR_OFF)
+#define VSCC_WEWS_OFF		4	/* 4: Write Enable on Write Status */
+#define VSCC_WEWS			(0x1 << VSCC_WEWS_OFF)
+					/* 5-7: reserved */
+#define VSCC_EO_OFF		8	/* 8-15: Erase Opcode */
+#define VSCC_EO				(0xff << VSCC_EO_OFF)
+#define VSCC_VCL_OFF		23	/* 23: Vendor Component Lock */
+#define VSCC_VCL			(0x1 << VSCC_VCL_OFF)
+					/* 24-31: reserved */
+
 // ICH9R SPI commands
 #define SPI_OPCODE_TYPE_READ_NO_ADDRESS		0
 #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS	1
@@ -305,6 +324,7 @@ static void pretty_print_opcodes(OPCODES *ops)
 }
 
 #define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF)
+#define pprint_reg_hex(reg, bit, val, sep) msg_pdbg("%s=0x%x" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF)
 static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
 {
 	msg_pdbg("HSFS: ");
@@ -348,6 +368,16 @@ static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
 	pprint_reg(SSFC, SCF, reg_val, "\n");
 }
 
+static void prettyprint_ich9_reg_vscc(uint32_t reg_val)
+{
+	pprint_reg_hex(VSCC, EBS, reg_val, ", ");
+	pprint_reg(VSCC, WG, reg_val, ", ");
+	pprint_reg(VSCC, WSR, reg_val, ", ");
+	pprint_reg(VSCC, WEWS, reg_val, ", ");
+	pprint_reg_hex(VSCC, EO, reg_val, ", ");
+	pprint_reg(VSCC, VCL, reg_val, "\n");
+}
+
 static uint8_t lookup_spi_type(uint8_t opcode)
 {
 	int a;
@@ -1312,6 +1342,17 @@ int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
 		ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
 		msg_pdbg("0xA0: 0x%08x (BBAR)\n",
 			     ichspi_bbar);
+
+		tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
+		msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp);
+		msg_pdbg("LVSCC: ");
+		prettyprint_ich9_reg_vscc(tmp);
+
+		tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
+		msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp);
+		msg_pdbg("UVSCC: ");
+		prettyprint_ich9_reg_vscc(tmp);
+
 		msg_pdbg("\n");
 		if (ichspi_desc) {
 			read_ich_descriptors_from_fdo(ich_spibar);
-- 
1.7.1