[flashrom] flashrom support for EP-9NPA7I
Colin L. Rice
dah4k0r at gmail.com
Mon Jun 20 05:54:31 CEST 2011
Sorry for missing you guys earlier. It works.
Note that this is an EP-9NPa7I. But eh whatever.
flashrom v0.9.3-r1338 on Linux 2.6.38-8-generic (x86_64), built with libpci
3.1.7, GCC 4.5.2, little endian
flashrom is free software, get the source code at http://www.flashrom.org
Calibrating delay loop... delay loop is unreliable, trying to continue OK.
Found chipset "NVIDIA CK804", enabling flash write... OK.
This chipset supports the following protocols: Non-SP.
Disabling flash write protection for board "EPoX EP-8NPA7I"... OK.
Found chip "SST SST49LF004A/B" (512 kB, FWH) at physical address 0xfff80000.
Flash image seems to be a legacy BIOS. Disabling coreboot-related checks.
Erasing and writing flash chip... Done.
Verifying flash... VERIFIED.
On Sun, Jun 19, 2011 at 4:51 PM, Stefan Tauner <
stefan.tauner at student.tuwien.ac.at> wrote:
> hello clr!
> you have missed carl-daniel or vice-versa one time and you never came
> back after that.
> i have dug up some info about the predecessor of your board i.e. 8NPA7I.
> the board enable that was executed on your machine by mistake is not
> complete (not even for the 8NPA7I) so it is expected to not work for
> i have not reverse engineered your bios (update tool), so i am not sure
> at all that the attached patch would help and not reboot/ruin/ignite
> your machine. but if you are brave you can try it.
> PS: this patch is not for merge, because we have no idea what 0x92
> really does imho. but we could incorporate this into a board enable
> function, if it really works or do you (fellow flashrom dev) think it is
> ok to just merge it as is?
> PPS: this is just a port of http://patchwork.coreboot.org/patch/2125/
> Kind regards/Mit freundlichen Grüßen, Stefan Tauner
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