[flashrom] [PATCH 3/3] add intel 6 series pci ids to chipset_enables
Uwe Hermann
uwe at hermann-uwe.de
Sat Jun 18 15:17:55 CEST 2011
On Mon, Jun 13, 2011 at 10:44:44PM +0200, Stefan Tauner wrote:
> as defined by Intel 6 Series Chipset and Intel C200 Series Chipset Specification Update;
> document number 324646-005, April 2011.
>
> Signed-off-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>
> ---
> chipset_enable.c | 14 ++++++++++++++
> 1 files changed, 14 insertions(+), 0 deletions(-)
>
> diff --git a/chipset_enable.c b/chipset_enable.c
> index 5907b86..a3ce942 100644
> --- a/chipset_enable.c
> +++ b/chipset_enable.c
> @@ -1121,6 +1121,20 @@ const struct penable chipset_enables[] = {
> {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
> {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
> {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
> + {0x8086, 0x1C46, NT, "Intel", "P67", enable_flash_ich10},
> + {0x8086, 0x1C47, NT, "Intel", "UM67", enable_flash_ich10},
> + {0x8086, 0x1C49, NT, "Intel", "HM65", enable_flash_ich10},
> + {0x8086, 0x1C4A, NT, "Intel", "H67", enable_flash_ich10},
> + {0x8086, 0x1C4B, NT, "Intel", "HM67", enable_flash_ich10},
> + {0x8086, 0x1C4C, NT, "Intel", "Q65", enable_flash_ich10},
> + {0x8086, 0x1C4D, NT, "Intel", "QS67", enable_flash_ich10},
> + {0x8086, 0x1C4E, NT, "Intel", "Q67", enable_flash_ich10},
> + {0x8086, 0x1C4F, NT, "Intel", "QM67", enable_flash_ich10},
> + {0x8086, 0x1C50, NT, "Intel", "B65", enable_flash_ich10},
> + {0x8086, 0x1C52, NT, "Intel", "C202", enable_flash_ich10},
> + {0x8086, 0x1C54, NT, "Intel", "C204", enable_flash_ich10},
> + {0x8086, 0x1C56, NT, "Intel", "C206", enable_flash_ich10},
> + {0x8086, 0x1C5C, NT, "Intel", "H61", enable_flash_ich10},
All hexnumbers lower-case, please (e.g. 0x1c46, not 0x1C46).
The entry for 0x1c44 (Z68) is missing (contained in the May 2011 PDF).
With the above changes:
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>
Uwe.
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