[flashrom] [coreboot] Flashrom -V output from E350M1/USB3

[Stefan Tauner]

On Sun, 05 Jun 2011 22:44:36 -0500
Marshall Buschman <mbuschman at lucidmachines.com> wrote:

> Here's the output. I have also successfully used flashrom on the E350M1 
> vanilla (without usb3).
> 
> fastboot ~ # flashrom -V
> flashrom v0.9.3-r1205 on Linux 2.6.39-delevi (x86_64), built with libpci 
> 3.1.7, GCC 4.4.5, little endian
> flashrom is free software, get the source code at http://www.flashrom.org
> 
> Calibrating delay loop... OS timer resolution is 1 usecs, 797M loops per 
> second, 10 myus = 10 us, 100 myus = 103 us,.
> Initializing internal programmer
> Found candidate at: 00000500-00000510
> Found coreboot table at 0x00000500.
> Found candidate at: 00000000-000001f8
> Found coreboot table at 0x00000000.
> coreboot table found at 0xc7ffe000.
> coreboot header(24) checksum: 3dea table(504) checksum: 2e62 entries: 14
> Vendor ID: ASROCK, part ID: E350M1
> DMI string system-manufacturer: ""
> DMI string system-product-name: ""
> DMI string system-version: ""
> DMI string baseboard-manufacturer: ""
> DMI string baseboard-product-name: ""
> DMI string baseboard-version: ""
> DMI string chassis-type: ""
> Found chipset "AMD SB700/SB710/SB750", enabling flash write... chipset 
> PCI ID is 1002:439d, SPI base address is at 00
> AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0
> PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1
> SpiArbEnable=0, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, 
> ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0
> NormSpeed is 16.5 MHz
> GPIO11 used for SPI_DO
> GPIO12 used for SPI_DI
> GPIO31 used for SPI_HOLD
> GPIO32 used for SPI_CS
> GPIO47 used for SPI_CLK
> SB700 IMC is not active.
> ROM strap override is not active
> OK.
> This chipset supports the following protocols: LPC,FWH,SPI.
> […]

so... amd kept the same pci id for their lpc device for the last years.
the e350m1 uses the A50m chipset, see
http://en.wikipedia.org/wiki/Comparison_of_AMD_chipsets#Comparison_of_FCH_.28Fusion_Controller_Hub.29
i think it is fairly save to change the chipset enable device_name to
something like "SB7x0/SB8x0/SB9x0/Axx(M/E)" or maybe
"SB[789]x0/A[57]x(M/E)"... but thats kinda unreadable. naming
all variants explicitly is not an option either. calling them
"predecessors of sb700" is not wise either (they probably WILL change
the id sometime in the future...).
what do you think?
-- 
Kind regards/Mit freundlichen Grüßen, Stefan Tauner