[flashrom] [PATCH] Support for Angelbird Wings PCIe SSD, Marvell 88SX7042

[Michael Karcher]

Am Freitag, den 04.02.2011, 02:35 +0100 schrieb Carl-Daniel Hailfinger:
> +	/* Get I/O BAR location. */
> +	tmp = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) &
> +	      PCI_BASE_ADDRESS_IO_MASK;
> +	/* Truncate to reachable range.
> +	 * FIXME: Check if the I/O BAR is actually reachable.
> +	 * This is an arch specific check.
> +	 */
> +	mv_iobar = tmp & 0xffff;
[...]
> +/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
> + * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
> + * This code only supports indirect accesses for now.
> + */
> +
> +/* Indirect access to via the I/O BAR1. */
> +static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
> +{
> +	/* 0x80000000 selects BAR2 for remapping. */
> +	OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
> +	OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
> +}

Do we need to call the I/O address region "BAR1" if its address is
stored at PCI_BASE_ADDRESS2? That sounds confusing.

Regards,
  Michael Karcher