[flashrom] [commit] r1405 - trunk

[repository service]

Author: stefanct
Date: Sat Aug  6 14:45:21 2011
New Revision: 1405
URL: http://flashrom.org/trac/flashrom/changeset/1405

Log:
Clear byte 0x92 of the LPC bridge for all CK804 (and MCP51) chipsets

The OEM BIOS on the EPoX EP-8PA7I and a number of other boards clear
byte 0x92 in the LPC bridge configuration space.  Do the same for
all CK804 chips, assuming this to be some sort of chipset-generic
write-enable.

Currently the same chipset enable is used for MCP51 (nForce 430).
There have been reports of successful writes with its variations
(e.g. A8N-LA (Nagami-GL8E)), but they were not tagged as OK. Due to
the new "unsupported chipset"-message we will get success reports in
the case this patch does not break anything on the MCP51-based boards.

See also:
http://www.flashrom.org/pipermail/flashrom/2011-July/007252.html
http://patchwork.coreboot.org/patch/3176/

Signed-off-by: Jonathan Kollasch <jakllsch at kollasch.net>
Acked-by: Joshua Roys <roysjosh at gmail.com>
Acked-by: Stefan Tauner <stefan.tauner at student.tuwien.ac.at>

Modified:
   trunk/chipset_enable.c

Modified: trunk/chipset_enable.c
==============================================================================
--- trunk/chipset_enable.c	Thu Aug  4 19:40:25 2011	(r1404)
+++ trunk/chipset_enable.c	Sat Aug  6 14:45:21 2011	(r1405)
@@ -801,6 +801,12 @@
 {
 	uint8_t old, new;
 
+	pci_write_byte(dev, 0x92, 0x00);
+	if (pci_read_byte(dev, 0x92) != 0x00) {
+		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY).\n", 0x92, 0x00, name);
+	}
+
 	old = pci_read_byte(dev, 0x88);
 	new = old | 0xc0;
 	if (new != old) {