[flashrom] [commit] r1290 - trunk

[repository service]

Author: mkarcher
Date: Sat Apr 30 00:11:36 2011
New Revision: 1290
URL: http://flashrom.org/trac/flashrom/changeset/1290

Log:
ichspi: Increase timeout to 60s for atomic operations

Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Modified:
   trunk/ichspi.c

Modified: trunk/ichspi.c
==============================================================================
--- trunk/ichspi.c	Wed Apr 27 16:34:08 2011	(r1289)
+++ trunk/ichspi.c	Sat Apr 30 00:11:36 2011	(r1290)
@@ -572,7 +572,14 @@
 	}
 	temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
 
-	/* Handle Atomic */
+	timeout = 100 * 60;	/* 60 ms are 9.6 million cycles at 16 MHz. */
+	/* Handle Atomic. Atomic commands include three steps:
+	    - sending the preop (mainly EWSR or WREN)
+	    - sending the main command
+	    - waiting for the busy bit (WIP) to be cleared
+	   This means the timeout must be sufficient for chip erase
+	   of slow high-capacity chips.
+         */
 	switch (op.atomic) {
 	case 2:
 		/* Select second preop. */
@@ -581,6 +588,7 @@
 	case 1:
 		/* Atomic command (preop+op) */
 		temp16 |= SPIC_ACS;
+		timeout = 100 * 1000 * 60;	/* 60 seconds */
 		break;
 	}
 
@@ -591,7 +599,6 @@
 	REGWRITE16(ICH7_REG_SPIC, temp16);
 
 	/* Wait for Cycle Done Status or Flash Cycle Error. */
-	timeout = 100 * 60;	/* 60 ms are 9.6 million cycles at 16 MHz. */
 	while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
 	       --timeout) {
 		programmer_delay(10);
@@ -711,7 +718,14 @@
 	}
 	temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
 
-	/* Handle Atomic */
+	timeout = 100 * 60;	/* 60 ms are 9.6 million cycles at 16 MHz. */
+	/* Handle Atomic. Atomic commands include three steps:
+	    - sending the preop (mainly EWSR or WREN)
+	    - sending the main command
+	    - waiting for the busy bit (WIP) to be cleared
+	   This means the timeout must be sufficient for chip erase
+	   of slow high-capacity chips.
+         */
 	switch (op.atomic) {
 	case 2:
 		/* Select second preop. */
@@ -720,6 +734,7 @@
 	case 1:
 		/* Atomic command (preop+op) */
 		temp32 |= SSFC_ACS;
+		timeout = 100 * 1000 * 60;	/* 60 seconds */
 		break;
 	}
 
@@ -730,7 +745,6 @@
 	REGWRITE32(ICH9_REG_SSFS, temp32);
 
 	/* Wait for Cycle Done Status or Flash Cycle Error. */
-	timeout = 100 * 60;	/* 60 ms are 9.6 million cycles at 16 MHz. */
 	while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) &&
 	       --timeout) {
 		programmer_delay(10);