[flashrom] [PATCH] ICH SPI paranoid error handling

[Michael Karcher]

Am Mittwoch, den 16.03.2011, 23:31 +0100 schrieb Stefan Reinauer:
> > Reduce SPI cycle timeout from 60 s to 60 ms.
Turned out to be a bad idea in the current code base. We use the preop
mechanism if it seems to fit, which means we use the ACS (atomic cycle
sequence) bit in the control register for that.

According to the ICH10 datasheet, the following operations are done
atomically:
 - sending the preop
 - sending the main opcode
 - polling the status register until WIP (bit 0) is low (!!!)

During all these operations, the SCIP (SPI cycle in progress) bit is
set.

So if enable write/sector erase is sent as "atomic sequence", the cycle
is only over after the erase completed, which can easily exceed 60ms.
See for example this report where exactly that happened:

http://paste.flashrom.org/view.php?id=513

We need to revert the timeout to 60 seconds at least if we use the
atomic sequence feature of the chipset. Or we need to stop using atomic
sequences.

Regards,
  Michael Karcher