[flashrom] flashrom: Can't mmap memory

Pádraig Brady P at draigBrady.com
Tue Sep 28 14:54:07 CEST 2010


This issue looks similar to this:
http://www.coreboot.org/pipermail/coreboot/2009-February/044672.html

Any ideas?
cheers,
Pádraig.

# /tmp/flashrom -V -c W25x80
flashrom v0.9.2-r1182 on Linux 2.6.32.10-90.fc12.i686 (i686), built with
libpci 2.2.4, GCC 4.1.3 20070929 (prerelease) (Ubuntu 4.1.2-16ubuntu2),
little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 5 usecs, 716M loops per
second, 10 myus = 10 us, 100 myus = 341 us, 1000 myus = 1126 us, 10000
myus = 9809 us, 20 myus = 20 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: " "
DMI string system-product-name: " "
DMI string system-version: " "
DMI string baseboard-manufacturer: " "
DMI string baseboard-product-name: "945GSE"
DMI string baseboard-version: " "
DMI string chassis-type: "Desktop"
Found chipset "Intel ICH7M", enabling flash write... chipset PCI ID is
8086:27b9,
0x7fffffff/0x7fffffff FWH IDSEL: 0x0
0x7fffffff/0x7fffffff FWH IDSEL: 0x0
0x7fffffff/0x7fffffff FWH IDSEL: 0x1
0x7fffffff/0x7fffffff FWH IDSEL: 0x1
0x7fffffff/0x7fffffff FWH IDSEL: 0x2
0x7fffffff/0x7fffffff FWH IDSEL: 0x2
0x7fffffff/0x7fffffff FWH IDSEL: 0x3
0x7fffffff/0x7fffffff FWH IDSEL: 0x3
0x7fffffff/0x7fffffff FWH IDSEL: 0x4
0x7fffffff/0x7fffffff FWH IDSEL: 0x5
0x7fffffff/0x7fffffff FWH IDSEL: 0x6
0x7fffffff/0x7fffffff FWH IDSEL: 0x7
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode disabled
0x7fffffff/0x7fffffff FWH decode disabled
0x7fffffff/0x7fffffff FWH decode disabled
0x7fffffff/0x7fffffff FWH decode disabled
Maximum FWH chip size: 0x100000 bytes
BIOS Lock Enable: enabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x3

Root Complex Register Block address = 0xfed1c000
GCS = 0xc20445: BIOS Interface Lock-Down: enabled, BOOT BIOS Straps: 0x1
(SPI)
Top Swap : not enabled
SPIBAR = 0xfed1c000 + 0x3020
0x00: 0x0008     (SPIS)
0x02: 0x4320     (SPIC)
0x04: 0x00000000 (SPIA)
0x08: 0x001430ef (SPID0)
0x0c: 0x00000000 (SPID0+4)
0x10: 0x00000000 (SPID1)
0x14: 0x00000000 (SPID1+4)
0x18: 0x00000000 (SPID2)
0x1c: 0x00000000 (SPID2+4)
0x20: 0x00000000 (SPID3)
0x24: 0x00000000 (SPID3+4)
0x28: 0x00000000 (SPID4)
0x2c: 0x00000000 (SPID4+4)
0x30: 0x00000000 (SPID5)
0x34: 0x00000000 (SPID5+4)
0x38: 0x00000000 (SPID6)
0x3c: 0x00000000 (SPID6+4)
0x40: 0x00000000 (SPID7)
0x44: 0x00000000 (SPID7+4)
0x50: 0x00000000 (BBAR)
0x54: 0x5006     (PREOP)
0x56: 0x463b     (OPTYPE)
0x58: 0x05d80302 (OPMENU)
0x5c: 0xc79f0190 (OPMENU+4)
0x60: 0x00000000 (PBR0)
0x64: 0x00000000 (PBR1)
0x68: 0x00000000 (PBR2)
0x6c: 0x00000000 (PBR3)

Programming OPCODES...
program_opcodes: preop=5006 optype=463b opmenu=05d80302c79f0190
done
SPI Read Configuration: prefetching disabled, caching enabled, OK.
This chipset supports the following protocols: SPI.
Probing for Winbond W25x80, 1024 KB: Error accessing flash chip,
0x100000 bytes at 0xfff00000
/dev/mem mmap failed: Value too large for defined data type





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