[flashrom] patch to add support for Xilinx parallel III/DLC5 programmer cable
Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006 at gmx.net
Tue Nov 30 03:06:35 CET 2010
Hi Peter,
thanks for your submission. I'm sorry you had to wait so long for an
answer. We were incredibly busy with an architectural change in flashrom
which required lots of testing.
On 18.09.2010 20:08, Jakab Peter wrote:
> I modified the rayer spi programmer source to be used with a Xilinx
> parallel III (also called DLC5) programmer cable.
>
> It's a trivial change of parallel port pins
>
I have reworked your pin definitions into a patch which allows us to use
one common driver for the RayeR SPI cable and the Xilinx DLC5 cable.
The rayer_spi driver defaults to the RayeR cable, and if you want to use
it for the Xilinx DLC5 cable, just use
flashrom -p rayer_spi:type=xilinx
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
If this patch works for you, please send a reply-to-all with
> Acked-by: Your name <your at email>
and I will commit the patch.
Regards,
Carl-Daniel
Index: flashrom-xilinx_dlc5/rayer_spi.c
===================================================================
--- flashrom-xilinx_dlc5/rayer_spi.c (Revision 1237)
+++ flashrom-xilinx_dlc5/rayer_spi.c (Arbeitskopie)
@@ -31,18 +31,25 @@
#if defined(__i386__) || defined(__x86_64__)
#include <stdlib.h>
+#include <string.h>
#include "flash.h"
#include "programmer.h"
+enum rayer_type {
+ TYPE_RAYER,
+ TYPE_XILINX_DLC5,
+};
+
/* We have two sets of pins, out and in. The numbers for both sets are
* independent and are bitshift values, not real pin numbers.
+ * Default settings are for the the RayeR hardware.
*/
/* Pins for master->slave direction */
-#define SPI_CS_PIN 5
-#define SPI_SCK_PIN 6
-#define SPI_MOSI_PIN 7
+static int rayer_cs_bit = 5;
+static int rayer_sck_bit = 6;
+static int rayer_mosi_bit = 7;
/* Pins for slave->master direction */
-#define SPI_MISO_PIN 6
+static int rayer_miso_bit = 6;
static uint16_t lpt_iobase;
@@ -51,22 +58,22 @@
static void rayer_bitbang_set_cs(int val)
{
- lpt_outbyte &= ~(1 << SPI_CS_PIN);
- lpt_outbyte |= (val << SPI_CS_PIN);
+ lpt_outbyte &= ~(1 << rayer_cs_bit);
+ lpt_outbyte |= (val << rayer_cs_bit);
OUTB(lpt_outbyte, lpt_iobase);
}
static void rayer_bitbang_set_sck(int val)
{
- lpt_outbyte &= ~(1 << SPI_SCK_PIN);
- lpt_outbyte |= (val << SPI_SCK_PIN);
+ lpt_outbyte &= ~(1 << rayer_sck_bit);
+ lpt_outbyte |= (val << rayer_sck_bit);
OUTB(lpt_outbyte, lpt_iobase);
}
static void rayer_bitbang_set_mosi(int val)
{
- lpt_outbyte &= ~(1 << SPI_MOSI_PIN);
- lpt_outbyte |= (val << SPI_MOSI_PIN);
+ lpt_outbyte &= ~(1 << rayer_mosi_bit);
+ lpt_outbyte |= (val << rayer_mosi_bit);
OUTB(lpt_outbyte, lpt_iobase);
}
@@ -75,7 +82,7 @@
uint8_t tmp;
tmp = INB(lpt_iobase + 1);
- tmp = (tmp >> SPI_MISO_PIN) & 0x1;
+ tmp = (tmp >> rayer_miso_bit) & 0x1;
return tmp;
}
@@ -89,14 +96,15 @@
int rayer_spi_init(void)
{
- char *portpos = NULL;
+ char *arg = NULL;
+ enum rayer_type rayer_type = TYPE_RAYER;
/* Non-default port requested? */
- portpos = extract_programmer_param("iobase");
- if (portpos) {
+ arg = extract_programmer_param("iobase");
+ if (arg) {
char *endptr = NULL;
unsigned long tmp;
- tmp = strtoul(portpos, &endptr, 0);
+ tmp = strtoul(arg, &endptr, 0);
/* Port 0, port >0x10000, unaligned ports and garbage strings
* are rejected.
*/
@@ -109,7 +117,7 @@
msg_perr("Error: iobase= specified, but the I/O base "
"given was invalid.\nIt must be a multiple of "
"0x4 and lie between 0x100 and 0xfffc.\n");
- free(portpos);
+ free(arg);
return 1;
} else {
lpt_iobase = (uint16_t)tmp;
@@ -120,11 +128,44 @@
/* Pick a default value for the I/O base. */
lpt_iobase = 0x378;
}
- free(portpos);
+ free(arg);
msg_pdbg("Using address 0x%x as I/O base for parallel port access.\n",
lpt_iobase);
+ arg = extract_programmer_param("type");
+ if (arg) {
+ if (!strcasecmp(arg, "rayer")) {
+ msg_pdbg("Using RayeR cable\n");
+ rayer_type = TYPE_RAYER;
+ } else if (!strcasecmp(arg, "xilinx")) {
+ msg_pdbg("Using Xilinx Parallel Cable III (DLC 5)\n");
+ rayer_type = TYPE_XILINX_DLC5;
+ } else {
+ msg_perr("Error: Invalid device type specified.\n");
+ free(arg);
+ return 1;
+ }
+ }
+ free(arg);
+ switch (rayer_type) {
+ case TYPE_RAYER:
+ /* Bits for master->slave direction */
+ rayer_cs_bit = 5;
+ rayer_sck_bit = 6;
+ rayer_mosi_bit = 7;
+ /* Bits for slave->master direction */
+ rayer_miso_bit = 6;
+ break;
+ case TYPE_XILINX_DLC5:
+ /* Bits for master->slave direction */
+ rayer_cs_bit = 2;
+ rayer_sck_bit = 1;
+ rayer_mosi_bit = 0;
+ /* Bits for slave->master direction */
+ rayer_miso_bit = 4;
+ }
+
get_io_perms();
/* Get the initial value before writing to any line. */
Index: flashrom-xilinx_dlc5/flashrom.8
===================================================================
--- flashrom-xilinx_dlc5/flashrom.8 (Revision 1237)
+++ flashrom-xilinx_dlc5/flashrom.8 (Arbeitskopie)
@@ -193,7 +193,7 @@
.BR "* dediprog" " (for SPI flash ROMs attached to a Dediprog SF100)"
.sp
.BR "* rayer_spi" " (for SPI flash ROMs attached to a RayeR parport \
-based programmer)"
+based programmer or a Xilinx DLC5)"
.sp
.BR "* nicintel_spi" " (for SPI flash ROMs attached to an Intel Gigabit \
network cards)"
@@ -430,7 +430,18 @@
is base I/O port address of the parallel port, which must be a multiple of
four. Make sure to not forget the "0x" prefix for hexadecimal port addresses.
.sp
-More information about the hardware is available at
+The default cable type is the RayeR cable. You can use the optional
+.B type
+parameter to specify the cable type with the
+.sp
+.B " flashrom \-p rayer_spi:type=model"
+.sp
+syntax where
+.B model
+can be
+.BR rayer " for the RayeR cable or " xilinx " for the Xilinx Parallel Cable III (DLC 5).
+.sp
+More information about the RayeR hardware is available at
http://rayer.ic.cz/elektro/spipgm.htm
.SH EXIT STATUS
flashrom exits with 0 on success, 1 on most failures but with 2 if /dev/mem
--
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