[flashrom] [commit] r1229 - trunk

[repository service]

Author: hailfinger
Date: Wed Nov 10 04:18:41 2010
New Revision: 1229
URL: http://flashrom.org/trac/flashrom/changeset/1229

Log:
ft2232_spi: allow 5x clock divisor to be set at runtime.
Check at init time whether the chip is a type 'H' (FT2232H or FT4232H).
If not, omit the disable-divide-by-5 (0x8a) command which can confuse
older chips.

Signed-off-by: Alex Badea <vamposdecampos at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Modified:
   trunk/ft2232_spi.c

Modified: trunk/ft2232_spi.c
==============================================================================
--- trunk/ft2232_spi.c	Wed Nov 10 04:10:41 2010	(r1228)
+++ trunk/ft2232_spi.c	Wed Nov 10 04:18:41 2010	(r1229)
@@ -46,11 +46,11 @@
  * The 'H' chips can run internally at either 12MHz or 60MHz.
  * The non-H chips can only run at 12MHz.
  */
-#define CLOCK_5X 1
+static uint8_t clock_5x = 1;
 
 /*
  * In either case, the divisor is a simple integer clock divider.
- * If CLOCK_5X is set, this divisor divides 30MHz, else it divides 6MHz.
+ * If clock_5x is set, this divisor divides 30MHz, else it divides 6MHz.
  */
 #define DIVIDE_BY 3  /* e.g. '3' will give either 10MHz or 2MHz SPI clock. */
 
@@ -131,6 +131,7 @@
 	int ft2232_type = FTDI_FT4232H_PID;
 	enum ftdi_interface ft2232_interface = INTERFACE_B;
 	char *arg;
+	double mpsse_clk;
 
 	arg = extract_programmer_param("type");
 	if (arg) {
@@ -186,6 +187,12 @@
 		exit(-1); // TODO
 	}
 
+	if (ftdic->type != TYPE_2232H && ftdic->type != TYPE_4232H) {
+		msg_pdbg("FTDI chip type %d is not high-speed\n",
+			ftdic->type);
+		clock_5x = 0;
+	}
+
 	if (ftdi_set_interface(ftdic, ft2232_interface) < 0) {
 		msg_perr("Unable to select interface: %s\n",
 				ftdic->error_str);
@@ -207,18 +214,16 @@
 		msg_perr("Unable to set bitmode to SPI\n");
 	}
 
-#if CLOCK_5X
-	msg_pdbg("Disable divide-by-5 front stage\n");
-	buf[0] = 0x8a;		/* Disable divide-by-5. */
-	if (send_buf(ftdic, buf, 1))
-		return -1;
-#define MPSSE_CLK 60.0
-
-#else
-
-#define MPSSE_CLK 12.0
+	if (clock_5x) {
+		msg_pdbg("Disable divide-by-5 front stage\n");
+		buf[0] = 0x8a;		/* Disable divide-by-5. */
+		if (send_buf(ftdic, buf, 1))
+			return -1;
+		mpsse_clk = 60.0;
+	} else {
+		mpsse_clk = 12.0;
+	}
 
-#endif
 	msg_pdbg("Set clock divisor\n");
 	buf[0] = 0x86;		/* command "set divisor" */
 	/* valueL/valueH are (desired_divisor - 1) */
@@ -227,8 +232,10 @@
 	if (send_buf(ftdic, buf, 3))
 		return -1;
 
-	msg_pdbg("SPI clock is %fMHz\n",
-		 (double)(MPSSE_CLK / (((DIVIDE_BY - 1) + 1) * 2)));
+	msg_pdbg("MPSSE clock: %f MHz divisor: %d "
+		 "SPI clock: %f MHz\n",
+		 mpsse_clk, DIVIDE_BY,
+		 (double)(mpsse_clk / (((DIVIDE_BY - 1) + 1) * 2)));
 
 	/* Disconnect TDI/DO to TDO/DI for loopback. */
 	msg_pdbg("No loopback of TDI/DO TDO/DI\n");