[flashrom] "ST M25P80" (1024 KB, SPI) - Tested - WORKS

[Harald Gutmann]

hargut at benchvice:~/flashrom$ sudo ./flashrom -w 
../coreboot.svn/build/coreboot.rom 
flashrom v0.9.3-r1223 on Linux 2.6.32-5-amd64 (x86_64), built with libpci 
3.1.7, GCC 4.4.5 20100913 (prerelease), little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
coreboot table found at 0x7fffe000.
Found ITE Super I/O, ID 0x8716.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
This chipset supports the following protocols: Non-SPI.
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
4 byte RDID not supported on this SPI controller
Found chip "ST M25P80" (1024 KB, SPI) at physical address 0xfff00000.
4 byte RDID not supported on this SPI controller
===
This flash part has status UNTESTED for operations: ERASE WRITE
The test status of this chip may have been updated in the latest development
version of flashrom. If you are running the latest development version,
please email a report to flashrom at flashrom.org if any of the above operations
work correctly for you with this flash part. Please include the flashrom
output with the additional -V option for all operations you tested (-V, -Vr,
-Vw, -VE), and mention which mainboard or programmer you tested.
Please mention your board in the subject line. Thanks for your help!
Erasing flash chip... SUCCESS.
Writing flash chip... COMPLETE.
Verifying flash... VERIFIED.          
hargut at benchvice:~/flashrom$