[flashrom] [PATCH] Support 2-byte SPI RES command

[Stefan Reinauer]

On 5/28/10 6:50 PM, Carl-Daniel Hailfinger wrote:
> Some chips implement the RES (0xab) opcode, but they use a non-standard
> two byte response instead of the usual one byte response.
> A two-byte response has the accuracy of REMS and RDID, so don't check
> for REMS/RDID availability before running a two-byte RES.
>
> Side note: The one-byte RES will fail on wbsio, but it did that in old
> versions as well. This needs to be fixed in wbsio.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   
Acked-by: Stefan Reinauer <stepan at coresystems.de>

flashrom v0.9.2-r1015 on Linux 2.6.32-22-server (x86_64), built with
libpci 3.0.0, GCC 4.4.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OK.
No coreboot table found.
Found chipset "Intel ICH7/ICH7R", enabling flash write... tried to set
0xdc to 0xb on ICH7/ICH7R failed (WARNING ONLY)
WARNING: SPI Configuration Lockdown activated.
FAILED!
This chipset supports the following protocols: SPI.
ich_spi_send_command: Address 0x000000 below allowed range 0xf80000-0xffffff
Found chip "SST SST25LF040A" (512 KB, SPI) at physical address 0xfff80000.
ich_spi_send_command: Address 0x000000 below allowed range 0xf80000-0xffffff
ich_spi_send_command: Address 0x000000 below allowed range 0xf80000-0xffffff
ich_spi_send_command: Address 0x000000 below allowed range 0xf80000-0xffffff
No operations were specified.


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