[flashrom] [commit] r960 - trunk

[repository service]

Author: snelson
Date: Sat Mar 20 04:01:19 2010
New Revision: 960
URL: http://flashrom.org/trac/coreboot/changeset/960

Log:
The Intel 28F001BX-T/B chips don't have block locks or mention of registers; chip is Old.
The Intel 28F004S5 mentions block locks which require a remapping registers.
Fixes problems brought up by carldani because of commit r948.
Signed-off-by: Sean Nelson <audiohacked at gmail.com>
Acked-by: Sean Nelson <audiohacked at gmail.com>

Modified:
   trunk/flashchips.c

Modified: trunk/flashchips.c
==============================================================================
--- trunk/flashchips.c	Sat Mar 20 00:01:34 2010	(r959)
+++ trunk/flashchips.c	Sat Mar 20 04:01:19 2010	(r960)
@@ -2316,7 +2316,6 @@
 		.model_id	= P28F001BXB,
 		.total_size	= 128,
 		.page_size	= 128 * 1024, /* 8k + 2x4k + 112k */
-		.feature_bits	= 0,
 		.tested		= TEST_BAD_WRITE,
 		.probe		= probe_jedec,
 		.probe_timing	= TIMING_ZERO,	/* Datasheet has no timing info specified */
@@ -2331,7 +2330,6 @@
 				.block_erase = erase_block_82802ab,
 			},
 		},
-		.unlock		= unlock_82802ab,
 		.write		= NULL,
 		.read		= read_memmapped,
 	},
@@ -2344,7 +2342,6 @@
 		.model_id	= P28F001BXT,
 		.total_size	= 128,
 		.page_size	= 128 * 1024, /* 112k + 2x4k + 8k */
-		.feature_bits	= 0,
 		.tested		= TEST_BAD_WRITE,
 		.probe		= probe_jedec,
 		.probe_timing	= TIMING_ZERO,	/* Datasheet has no timing info specified */
@@ -2359,7 +2356,6 @@
 				.block_erase = erase_block_82802ab,
 			},
 		},
-		.unlock		= unlock_82802ab,
 		.write		= NULL,
 		.read		= read_memmapped,
 	},
@@ -2372,6 +2368,7 @@
 		.model_id	= E_28F004S5,
 		.total_size	= 512,
 		.page_size	= 256,
+		.feature_bits	= FEATURE_REGISTERMAP,
 		.tested		= TEST_UNTESTED,
 		.probe		= probe_82802ab,
 		.probe_timing	= TIMING_ZERO,	/* Datasheet has no timing info specified */