[flashrom] [PATCH 02/11] Rebased Board Enable Patch: Abit VT6X4
Sean Nelson
audiohacked at gmail.com
Fri Mar 19 23:27:05 CET 2010
This board has *no* usable IDs at all, neither DMI nor PCI
subsystem IDs. You have to force it using "-m abit:vt6x4"
Try 3: really correct polarity of the GPIO
Signed-off-by: Michael Karcher <flashrom at mkarcher.dialup.fu-berlin.de>
---
board_enable.c | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/board_enable.c b/board_enable.c
index 9ac5653..7b1fa12 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -1009,26 +1009,34 @@ static int board_soyo_sy_7vca(const char *name)
/* PM IO base */
base = pci_read_long(dev, 0x48) & 0x0000FF00;
/* Drop GPO0 */
tmp = INB(base + 0x4C);
tmp &= ~0x01;
OUTB(tmp, base + 0x4C);
return 0;
}
/**
+ * Suited for Abit VT6X5: Pro133x + VT82C686A
+ */
+static int via_apollo_gpo4_lower(const char *name)
+{
+ return via_apollo_gpo_set(4, 0);
+}
+
+/**
* Enable some GPIO pin on SiS southbridge.
* Suited for MSI 651M-L: SiS651 / SiS962
*/
static int board_msi_651ml(const char *name)
{
struct pci_dev *dev;
uint16_t base, temp;
dev = pci_dev_find(0x1039, 0x0962);
if (!dev) {
fprintf(stderr, "Expected south bridge not found\n");
return 1;
}
@@ -1253,26 +1261,27 @@ static int it8712f_gpio3_1_raise(const char *name)
* legacy bios is installed and when autodetection is not possible, these ids
* can be used to identify the board through the -m command line argument.
*
* When a board is identified through its coreboot ids (in both cases), the
* main pci ids are still required to match, as a safeguard.
*/
/* Please keep this list alphabetically ordered by vendor/board name. */
struct board_pciid_enable board_pciid_enables[] = {
/* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
{0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise},
{0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
+ {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, NT, via_apollo_gpo4_lower},
{0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
{0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
{0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
{0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e},
{0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e},
{0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
{0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x},
{0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
{0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25},
{0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
--
1.6.6
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