[flashrom] [PATCH] RayeR speedups, variable port
Idwer Vollering
vidwer at gmail.com
Wed Jul 21 16:35:12 CEST 2010
2010/7/21 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> Speed up RayeR SPIPGM driver in flashrom by a factor of 2.
>
> Allow specification of an alternate base port with
> flashrom -p rayer_spi:lptport=0x278
> Any port number is allowed as long as it is nonzero, below 65536 and a
> multiple of four.
>
> Untested, should work.
>
> Martin, this one should hopefully reach the speed of SPIPGM.exe for
> reads. I'll ask Idwer to provide a DOS binary for you.
>
http://khepri.coresystems.de/~idwer/flashrom/r1093-patchwork-1666/
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>
> Index: flashrom-bitbang_spi_rayer_faster/flashrom.8
> ===================================================================
> --- flashrom-bitbang_spi_rayer_faster/flashrom.8 (Revision 1093)
> +++ flashrom-bitbang_spi_rayer_faster/flashrom.8 (Arbeitskopie)
> @@ -394,7 +394,18 @@
> (in Hz). The default is the maximum frequency of 8 MHz.
> .TP
> .BR "rayer_spi " programmer
> -No parameters defined yet. More information about the hardware is
> available at
> +The default I/O base address used for the parallel port is 0x378 and you
> can use
> +the optional
> +.B lptport
> +parameter to specify an alternate base I/O address with the
> +.sp
> +.B " flashrom \-p rayer_spi:lptport=portnum"
> +.sp
> +syntax where
> +.B portnum
> +is the I/O port number of your parallel port which must be a multiple of
> 4.
> +.sp
> +More information about the hardware is available at
> http://rayer.ic.cz/elektro/spipgm.htm
> .SH EXIT STATUS
> flashrom exits with 0 on success, 1 on most failures but with 2 if
> /dev/mem
> Index: flashrom-bitbang_spi_rayer_faster/rayer_spi.c
> ===================================================================
> --- flashrom-bitbang_spi_rayer_faster/rayer_spi.c (Revision 1093)
> +++ flashrom-bitbang_spi_rayer_faster/rayer_spi.c (Arbeitskopie)
> @@ -30,6 +30,7 @@
> */
> #if defined(__i386__) || defined(__x86_64__)
>
> +#include <stdlib.h>
> #include "flash.h"
>
> /* We have two sets of pins, out and in. The numbers for both sets are
> @@ -42,7 +43,7 @@
> /* Pins for slave->master direction */
> #define SPI_MISO_PIN 6
>
> -static int lpt_iobase;
> +static uint16_t lpt_iobase;
>
> /* FIXME: All rayer_bitbang_set_* functions could use caching of the value
> * stored at port lpt_iobase to avoid unnecessary INB. In theory, only one
> @@ -50,37 +51,31 @@
> * value.
> */
>
> -void rayer_bitbang_set_cs(int val)
> +/* Cached value of last byte sent. */
> +static uint8_t lpt_outval;
> +
> +static void rayer_bitbang_set_cs(int val)
> {
> - uint8_t tmp;
> -
> - tmp = INB(lpt_iobase);
> - tmp &= ~(1 << SPI_CS_PIN);
> - tmp |= (val << SPI_CS_PIN);
> - OUTB(tmp, lpt_iobase);
> + lpt_outval &= ~(1 << SPI_CS_PIN);
> + lpt_outval |= (val << SPI_CS_PIN);
> + OUTB(lpt_outval, lpt_iobase);
> }
>
> -void rayer_bitbang_set_sck(int val)
> +static void rayer_bitbang_set_sck(int val)
> {
> - uint8_t tmp;
> -
> - tmp = INB(lpt_iobase);
> - tmp &= ~(1 << SPI_SCK_PIN);
> - tmp |= (val << SPI_SCK_PIN);
> - OUTB(tmp, lpt_iobase);
> + lpt_outval &= ~(1 << SPI_SCK_PIN);
> + lpt_outval |= (val << SPI_SCK_PIN);
> + OUTB(lpt_outval, lpt_iobase);
> }
>
> -void rayer_bitbang_set_mosi(int val)
> +static void rayer_bitbang_set_mosi(int val)
> {
> - uint8_t tmp;
> -
> - tmp = INB(lpt_iobase);
> - tmp &= ~(1 << SPI_MOSI_PIN);
> - tmp |= (val << SPI_MOSI_PIN);
> - OUTB(tmp, lpt_iobase);
> + lpt_outval &= ~(1 << SPI_MOSI_PIN);
> + lpt_outval |= (val << SPI_MOSI_PIN);
> + OUTB(lpt_outval, lpt_iobase);
> }
>
> -int rayer_bitbang_get_miso(void)
> +static int rayer_bitbang_get_miso(void)
> {
> uint8_t tmp;
>
> @@ -99,16 +94,49 @@
>
> int rayer_spi_init(void)
> {
> - /* Pick a default value for now. */
> - lpt_iobase = 0x378;
> + char *portpos = NULL;
>
> + /* Non-default port requested? */
> + portpos = extract_programmer_param("lptport");
> + if (portpos) {
> + char *endptr = NULL;
> + unsigned long tmp;
> + tmp = strtoul(portpos, &endptr, 0);
> + /* Port 0, port >0x1000, unaligned ports and garbage
> strings
> + * are rejected.
> + */
> + if (!tmp || (tmp >= 0x10000) || (tmp & 0x3) ||
> + (*endptr != '\0')) {
> + /* Using ports below 0x100 is a really bad idea,
> and
> + * should only be done if no port between 0x100 and
> + * 0xfffc works due to routing issues.
> + */
> + msg_perr("Error: lptport specified, but no valid "
> + "port specified.\nPort must be a multiple
> of "
> + "0x4 and lie between 0x100 and
> 0xfffc.\n");
> + free(portpos);
> + return 1;
> + } else {
> + lpt_iobase = (uint16_t)tmp;
> + msg_pinfo("Non-default I/O base requested. This
> will "
> + "not change the hardware settings.\n");
> + }
> + } else {
> + /* Pick a default value for the I/O base. */
> + lpt_iobase = 0x378;
> + }
> + free(portpos);
> +
> msg_pdbg("Using port 0x%x as I/O base for parallel port access.\n",
> lpt_iobase);
>
> get_io_perms();
>
> - /* 1 usec halfperiod delay for now. */
> - if (bitbang_spi_init(&bitbang_spi_master_rayer, 1))
> + /* Get the initial value before writing to any line. */
> + lpt_outval = INB(lpt_iobase);
> +
> + /* Zero halfperiod delay. */
> + if (bitbang_spi_init(&bitbang_spi_master_rayer, 0))
> return 1;
>
> buses_supported = CHIP_BUSTYPE_SPI;
>
>
> --
> http://www.hailfinger.org/
>
>
> _______________________________________________
> flashrom mailing list
> flashrom at flashrom.org
> http://www.flashrom.org/mailman/listinfo/flashrom
>
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