[flashrom] [commit] r1089 - trunk

repository service svn at flashrom.org
Sun Jul 18 00:42:34 CEST 2010


Author: hailfinger
Date: Sun Jul 18 00:42:33 2010
New Revision: 1089
URL: http://flashrom.org/trac/coreboot/changeset/1089

Log:
Use the BAR value returned by pcidev_init which automatically applies
the correct BAR mask for the drkaiser driver.
Truncate flash chip addresses to fit into the 128 kB memory window for
drkaiser and pick the same window size for gfxnvidia.

Uwe tested all operations successfully on a Dr. Kaiser card.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>

Modified:
   trunk/drkaiser.c
   trunk/gfxnvidia.c

Modified: trunk/drkaiser.c
==============================================================================
--- trunk/drkaiser.c	Sun Jul 18 00:28:05 2010	(r1088)
+++ trunk/drkaiser.c	Sun Jul 18 00:42:33 2010	(r1089)
@@ -26,6 +26,9 @@
 #define PCI_MAGIC_DRKAISER_ADDR		0x50
 #define PCI_MAGIC_DRKAISER_VALUE	0xa971
 
+/* Mask to restrict flash accesses to the 128kB memory window. */
+#define DRKAISER_MEMMAP_MASK		((1 << 17) - 1)
+
 const struct pcidev_status drkaiser_pcidev[] = {
 	{0x1803, 0x5057, OK, "Dr. Kaiser", "PC-Waechter (Actel FPGA)"},
 	{},
@@ -39,16 +42,13 @@
 
 	get_io_perms();
 
-	pcidev_init(PCI_VENDOR_ID_DRKAISER, PCI_BASE_ADDRESS_2,
-		    drkaiser_pcidev);
+	addr = pcidev_init(PCI_VENDOR_ID_DRKAISER, PCI_BASE_ADDRESS_2,
+			   drkaiser_pcidev);
 
 	/* Write magic register to enable flash write. */
 	pci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR,
 		       PCI_MAGIC_DRKAISER_VALUE);
 
-	/* TODO: Mask lower bits? How many? 3? 7? */
-	addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) & ~0x03;
-
 	/* Map 128KB flash memory window. */
 	drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory",
 			       addr, 128 * 1024);
@@ -69,10 +69,10 @@
 
 void drkaiser_chip_writeb(uint8_t val, chipaddr addr)
 {
-	mmio_writeb(val, drkaiser_bar + addr);
+	mmio_writeb(val, drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK));
 }
 
 uint8_t drkaiser_chip_readb(const chipaddr addr)
 {
-	return mmio_readb(drkaiser_bar + addr);
+	return mmio_readb(drkaiser_bar + (addr & DRKAISER_MEMMAP_MASK));
 }

Modified: trunk/gfxnvidia.c
==============================================================================
--- trunk/gfxnvidia.c	Sun Jul 18 00:28:05 2010	(r1088)
+++ trunk/gfxnvidia.c	Sun Jul 18 00:42:33 2010	(r1089)
@@ -25,6 +25,11 @@
 
 #define PCI_VENDOR_ID_NVIDIA	0x10de
 
+/* Mask to restrict flash accesses to a 128kB memory window.
+ * FIXME: Is this size a one-fits-all or card dependent?
+ */
+#define GFXNVIDIA_MEMMAP_MASK		((1 << 17) - 1)
+
 uint8_t *nvidia_bar;
 
 const struct pcidev_status gfx_nvidia[] = {
@@ -95,10 +100,10 @@
 
 void gfxnvidia_chip_writeb(uint8_t val, chipaddr addr)
 {
-	mmio_writeb(val, nvidia_bar + addr);
+	mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
 }
 
 uint8_t gfxnvidia_chip_readb(const chipaddr addr)
 {
-	return mmio_readb(nvidia_bar + addr);
+	return mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
 }




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