[flashrom] [PATCH] Fix PIIX4 GPO set

Michael Karcher flashrom at mkarcher.dialup.fu-berlin.de
Tue Feb 16 18:43:06 CET 2010

[copied to the mailing list]

Am Dienstag, den 16.02.2010, 10:23 -0600 schrieb Zach Stuart:
> Here is the latest flashrom -V output.
> Disabling flash write protection for board "Intel SE440BX-2"... Port 8037 was 6f
> should be set to 67 and is now 6f
> OK.
The "OK" might be fixed, as it is not OK, because the value read after
writing is not the value written.

The code that produced this output has not appeared on the mailing list,
so I include it here for reference:

|        /* PM IO base */
|        base = pci_read_long(dev, 0x40) & 0x0000FFC0;
|        gpo_byte = gpo >> 3;
|        gpo_bit = gpo & 7;
|        tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
|        msg_pdbg("Port %04x was %02x\n", base + 0x34 + gpo_byte, tmp);
|        if (raise)
|                tmp |= 0x01 << gpo_bit;
|        else
|                tmp &= ~(0x01 << gpo_bit);
|        OUTB(tmp, base + 0x34 + gpo_byte);
|        msg_pdbg("should be set to %02x and is now %02x\n", tmp, INB(base+0x34+gpo_byte));

Anyone got an idea what could be wrong here?

The following ideas have already been rejected:

1) The pin is configured as input
  Rejected because: On the PIIX4, there are no GPIOs, GPI and GPO are on
different pins.

2) Multiplexing of pins makes this GPO not available
  Rejected because: GPO27 is not multiplexed

3) The write to the GPO port is trapped.
  Rejected because: The datasheet doesn't tell anything about
trapability or making the GPO register read only.

4) You need a special magic dance to write to this register
  Rejected because: The SMI code from that board does a plain
and operation just like we do, without a magic dance. Of course, SMM is
a different execution environment than flashrom userspace, but the
datasheet doesn't mention anything about availability only in SMM.

  Michael Karcher

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