[flashrom] multiple spi chips and controllers question

[Andriy Gapon]

[Subject line continuation: Gigabyte motherboard with DualBIOS]

Result of 'flashrom -V' on my machine:
flashrom v0.9.1-r710
No coreboot table found.
Found chipset "AMD SB700/SB710/SB750", enabling flash write... SPI base address
is at 0xfec10000
AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0

PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1

SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4,
SpiBridgeDisable=0, DropOneClkOnRd=0
GPIO11 used for SPI_DO

GPIO12 used for SPI_DI

GPIO31 used for SPI_HOLD

GPIO32 used for SPI_CS

GPIO47 used for SPI_CLK

ROM strap override is not active

OK.

This chipset supports the following protocols: LPC,FWH,SPI.

Disabling flash write protection for board "GIGABYTE GA-MA78GM-S2H"... Serial
flash segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled

Serial flash segment 0xffee0000-0xffefffff disabled

Serial flash segment 0xfff80000-0xfffeffff enabled

LPC write to serial flash enabled

Serial flash pin 29

Serial flash port 0x0238

OK.

[...]
Probing for SST SST25VF080B, 1024 KB: RDID returned 0xbf 0x25 0x8e.
probe_spi_rdid_generic: id1 0xbf, id2 0x258e

Chip status register is 00

Chip status register: Block Protect Write Disable (BPL) is not set

Chip status register: Auto Address Increment Programming (AAI) is not set

Chip status register: Bit 5 / Block Protect 3 (BP3) is not set

Chip status register: Bit 4 / Block Protect 2 (BP2) is not set

Chip status register: Bit 3 / Block Protect 1 (BP1) is not set

Chip status register: Bit 2 / Block Protect 0 (BP0) is not set

Chip status register: Write Enable Latch (WEL) is not set

Chip status register: Write In Progress (WIP/BUSY) is not set

Found chip "SST SST25VF080B" (1024 KB, SPI) at physical address 0xfff00000.

[...]


First, one note: shouldn't there be a new line after '-S2H"...' and before 'Serial'?

Second, an easy question - what does the following line means?
Serial flash segment 0xffee0000-0xffefffff disabled
Does it mean that LPC cycles for that address range won't reach SPI flash
neither for reading nor for writing? And so I won't be able to flash some part
of the chip? Or is it something else?

Third, the main question.
I understand that SB700 has an embedded SPI controller and flashrom first
discovers it and prints its configuration.
There is also IT8718S chip on this motherboard which has SPI controller as well,
and it looks like flashrom also discovers it.
Q: which controller flashrom uses next to discover the SPI flash chip?

The reason I am asking - this mainboard has Gigabyte DualBIOS feature
("non-virtual"), and there are two physical SPI flash chips on the board.
I am curious as to how they are wired.
Are they wired to different controllers? Or the same one - then which one?
Can I access both of them?
Does anybody know about that or has a reasonable guess?

Thank you very much in advance!
And sorry for so many question marks.

-- 
Andriy Gapon